Re: [SI-LIST] : An Interesting Presentation

Laurence Michaels (lmichael@techmail.gdc.com)
Tue, 20 Apr 1999 09:28:42 -0400

One of the things a slower bus timing (with less stringent timing
requirements at RAM chip inputs for instance), is that it allows for
more ringing, and other things that are bad from an SI viewpoint.
There's more time for the data signals to settle down to a reasonable
state before the data gets clocked in.

So, in buses with loose timing requirements, SI is almost ignorable on
data lines, as long as the clocks are good, and the data has enough time
to settle.

Clock tree design is left as an exercise for the reader.

Comments?

-- Laurence

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