Chip-level decoupling won't help with your SSO, although it will
keep the onchip (core) supply in better shape. I most
profoundly hope you're using reasonable packages such as the
copper-slug cavity-down ball grid parts (what we call HBGA).
You REALLY need the low theta(jc) and low pin inductance.
My first suggestion is to ditch the 5v supply. You're paying a
premium for obsolete parts and then having to pour in more than
twice the power compared to 3.3v parts -- and in your case that
power density is a show-stopper. Of course, you probably can't
change it by now. Bummer.
> At this high of power level, what are the primary concerns?
Desoldering the ICs. Delaminating the PWB.
> do we best address them? Is there a limit on how much current
> a half-ounce copper sheet in FR4 can tolerate?
Yup, and you're probably way past it. Pay particular attention
to the power path through your via field around the ICs; we've
seen some parts suck enough juice to blister the FR4 on much
lower-power applications than yours. If at all possible go
to multiple power planes with 2 oz copper. Not only will you
get better power distribution but it'll spread the heat somewhat
> How much current
> can I push through a standard via before it melts?
More than you can afford in terms of IR and Ldi/dt drop.
The vias aren't the worst of the bottleneck; it's the gaps
between them that are likely to kill ya.
> How can
> we effectively remove the heat?
Water jackets. Freon immersion.
Look, I'm not joking. 1000w is the kind of power that you use
for heating a small room. With a high-velocity fan behind it
my little ceramic heater still glows cherry red with 750 watts;
you are going to need a large external chiller to keep under
150C junction temps with anything aircooled.
-- D. C. Sessions email@example.com
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