It depends broadly on following things:
(a) what kind of package: ground return path within the package is different
for different types of packages (stack-up of the package dictates this). In
BGA type packages
there are usually metal islands for gnd and pwr(connected to their
respective power/ground planes thorough vias), you can isolate other noises
assigning a separate island to clock power/ground (if you have such a case)
In the past I have assigned two dedicated pads for power and ground around
clock pad within AISC.
Also it is helpful to put quiet buffers around a clock pad. This is also
dependent upon the fact how your power distribution is with the chip.
(b) Clock type (is it differential), noise sensitivity, drive strength etc:
If clock net is very noise sensitive then you can provide noise isolation at
package level by customizing the power/ground planes. But you might have to
effective improvement by field solvers and SI tools.
you can isolate power/ground distribution at chip level as well if you have
Signal Integrity Engineer
Dell Computers Corporation, TX
From: chenlanbing [mailto:firstname.lastname@example.org]
Sent: Saturday, July 17, 1999 4:54 AM
Subject: [SI-LIST] : How to treat the ASIC package pin-assigns
Now I have a ASIC package design.There is a lot of data bus and a clock
signal in this package.
How can I do the pin assigns?If I put the clock pin beside the data pins and
insert a gnd pin,can it improve the SI?
I need your helps and wish can get some advices about how to pin assign the
ASIC package.I know it is very key in HSSD to pin assign the connector and I
can get a good pin assign by simulation.
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