Re: [SI-LIST] : SCSI-LVDS Models

fabrizio zanella (fzanella@fishbowl02.lss.emc.com)
Tue, 29 Jun 1999 10:43:25 -0400

I agree Joe, good point. I had a problem last year running backplane
simulations with LVDS drivers and receivers, and the only solution which
worked was to ramp VCC slowly.
Michael, I had to do the following:

VCC VCC_1 0 pulse (0 3.3v 0ns 10ns 10ns 1ns 2ns)
Use VCC_1 as the vcc connection for your drivers and receivers.
In my situation, using HSPICE, I did not see a steady state LVDS output
until after 300ns.

Regards,

Fabrizio Zanella
EMC, Hardware Engineering
fzanella@emc.com
508-435-2075, x4645
-------------
Original Text
From: <jjcahill@us.ibm.com>, on 6/29/99 10:11 AM:
To: smtp@Eng@EMCHOP1[<si-list@silab.eng.sun.com>]
Cc: smtp@Eng@EMCHOP1[<Michael.Chan@compaq.com>]

Many differential receivers have circuits with high gain or even positive
feedback, each of which can cause convergence problems for simulators.
Review
the circuit to determine if it has those characteristics. If I encounter a
circuit that the simulator has trouble determining a DC state for I start
the
signal sources and power supply voltages at 0 to make the DC state solution
trivial and then slowly ramp the sources and supplies to the intended
starting
point, letting it settle there and then doing the interesting portion of
the
simulation. Simulator transient solution algorithms seem to be better at
handling dynamic behavior in the circuit than the dc algorithms. Specifying
the
initial conditions for crucial nodes and elements in the circuit is another
way
to aid the DC algorithm, but you must get the correct 'crucial' nodes or
you
will have continuing convergence problems.

Joe

CEC Analysis and I/O Design
Phone: 507.253.0762 Fax: 507.253.4966
jjcahill@us.ibm.com

"Chan, Michael " <Michael.Chan@COMPAQ.com> on 06/28/99 02:18:28 PM

Please respond to si-list@silab.eng.sun.com

To: "'si-list@silab.eng.sun.com'" <si-list@silab.eng.sun.com>
cc: (bcc: Joe Cahill/Rochester/IBM)
Subject: [SI-LIST] : SCSI-LVDS Models

Hi SI Guru:
We are trying to do some Hspice simulations on SCSI bus to
investigate signal quality. One problem that we encountered is the
convergence
problem of Hspice. We are still not sucessful in bringing the spice
simulation to converge after we have tried different convergence aids as
suggested in
the Hspice manual. We plan to replace most of the receiver models with
passive lumped models ( i.e. one resistor and one capacitor for CMOS input
buffer ) and see whether this will help. Can anyone suggest what an
equivalent model will be for a LVDS input receiver will be? Any suggestion
will be appreciated.

Regards,
Michael Chan
Compaq Computer Corp.
Michael.Chan@compaq.com

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