[email protected] wrote:
> Shoot! I was out of town and missed one of the most interesting discussions of
> the year! (Plane-jumping return currents) So at the risk of re-opening this
> thread, filling all your mailboxes again, and being branded an outcast, here
> goes. (Remember, that delete button is only a few inches away...)
>
> You're all familiar with this picture of high-frequency return current bunching
> up under the signal trace, right? According to the picture, it dies off pretty
> quickly as you move along the x-axis away from the trace. Well, I've been
> considering rules for the area density of ground vias and decoupling capacitors,
> and it occurs to me that if this picture were true, then the only place for a
> ground via or capacitor is within 2-3 trace widths of the signal via in
> question. (Which is, for most of our applications, absurd.) Otherwise I'd be
> forcing the return current out of that very tight loop, increasing the
> inductance, adding a discontinuity, generating plane noise, emissions, and all
> those nasty things.
> The ground plane you are working with is not in a vacuum. Recognizing
that all the power and ground planes in a board have capacitance between them
which can be modeled as a matrix of capacitors, when the signal changes layers
the ground/power planes are connected together at higher frequencys. This is not
a hard connection but through an impedance. The vias that were considered between
planes were there to reduce this impedance between the ground layers at that point.
> Now, I know that boards work quite well up to a few hundred
> MHz with considerably less than 100 de-caps per square inch! So where's the
> discrepancy? Is there a hole in my fairly simplistic, qualitative analysis? Or
> is this just like everything else: knowing how some parameter varies between
> the end cases is much harder than analyzing the end cases?
>
> On another tangent, I believe 2-D field solvers make the assumption that the
> return current is evenly distributed across the surface of a plane when you ask
> them to compute C, L and Z for a given cross-section. Doesn't this also
> conflict with the high-frequency current distribution picture?
>
> Eagerly awaiting your answers and hoping I have time to read them,
>
> Greg Edlund
> Advisory Engineer, Critical Net Analysis
> IBM
> 3650 Hwy. 52 N, Dept. HDC
> Rochester, MN 55901
> [email protected]
>
> **** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
-- Ronald B. Miller _\\|//_ Signal Integrity Engineer (408)487-8017 (' 0-0 ') fax(408)487-8017 ==========0000-(_)0000=========== Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131 [email protected], [email protected]
--------------26523BD81E215613E068A4AB Content-Type: text/html; charset=us-ascii Content-Transfer-Encoding: 7bit
<!doctype html public "-//w3c//dtd html 4.0 transitional//en"> [email protected] wrote:
Shoot! I was out of town and missed one of the most interesting discussions of
the year! (Plane-jumping return currents) So at the risk of re-opening this
thread, filling all your mailboxes again, and being branded an outcast, here
goes. (Remember, that delete button is only a few inches away...)You're all familiar with this picture of high-frequency return current bunching
up under the signal trace, right? According to the picture, it dies off pretty
quickly as you move along the x-axis away from the trace. Well, I've been
considering rules for the area density of ground vias and decoupling capacitors,
and it occurs to me that if this picture were true, then the only place for a
ground via or capacitor is within 2-3 trace widths of the signal via in
question. (Which is, for most of our applications, absurd.) Otherwise I'd be
forcing the return current out of that very tight loop, increasing the
inductance, adding a discontinuity, generating plane noise, emissions, and all
those nasty things.The ground plane you are working with is not in a vacuum. Recognizingthat all the power and ground planes in a board have capacitance between them
which can be modeled as a matrix of capacitors, when the signal changes layers
the ground/power planes are connected together at higher frequencys. This is not
a hard connection but through an impedance. The vias that were considered between
planes were there to reduce this impedance between the ground layers at that point.
Now, I know that boards work quite well up to a few hundred
MHz with considerably less than 100 de-caps per square inch! So where's the
discrepancy? Is there a hole in my fairly simplistic, qualitative analysis? Or
is this just like everything else: knowing how some parameter varies between
the end cases is much harder than analyzing the end cases?On another tangent, I believe 2-D field solvers make the assumption that the
return current is evenly distributed across the surface of a plane when you ask
them to compute C, L and Z for a given cross-section. Doesn't this also
conflict with the high-frequency current distribution picture?Eagerly awaiting your answers and hoping I have time to read them,
Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
[email protected]**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
-- Ronald B. Miller _\\|//_ Signal Integrity Engineer (408)487-8017 (' 0-0 ') fax(408)487-8017 ==========0000-(_)0000=========== Brocade Communications Systems, 1901 Guadalupe Parkway, San Jose, CA 95131 [email protected], [email protected]--------------26523BD81E215613E068A4AB-- **** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****