# Re: [SI-LIST] : Routing Criteria

Lum Wee Mei ([email protected])
Tue, 27 Jul 1999 07:40:13 +0800

--------------FEE29DAC38925F71488282D4
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Thank you very much for being the only repsonse to my questions. I
appreciate the answers and clear explanation.

Regards,
Wee Mei

Steve Weir wrote:

> Q1. You need to limit the crosstalk. Barring purchase of a
> crosstalk analysis tool, you can estimate the worst case crosstalk as:
>
> CT = 1 / ( 1 + ( x/h )^ 2 ), where x is the center to center distance
> between parallel traces on the same layer, and h is the distance from
> the center of the signal etch to the center of the nearest reflection
> plane, sic where the opposing return current flows.
>
> For example, if you have 5 mils between a given signal layer and the
> nearest ground plane, then your edge-coupled crosstalk will not get
> worse than 10% for 15 mil spacing. Broad-face crosstalk is similar,
> replacing x with the height between adjacent signal layers. Assuming
> that you have packed most traces on 10 mil centers, then you can route
> one extra phantom trace between the address block, and data block to
> maintain a total of 20 mils, which will yield x/h of 1/4, or a
> crosstalk of 1/17, < 6%. You can use the same technique for clocks,
> and any other signal which will be used to set timing.
>
> The signals which remain close together may exhibit crosstalk as high
> as 20% if the traces run parallel for much more than 1/2 wavelength.
> which switch to opposing states will take longer to settle.
>
> In crude terms, each line acts as a winding in a pulse transformer
> both inducing current into the adjacent trace, and receiving current
> from the adjacent trace. This reduces the current available to charge
> the capacitance along the line, increasing the time before the far-end
> matches the near-end.
>
> If you are pushing frequency limits, you either need decent analysis
> software, your design will be overly conservative, or your design will
> be risky.
>
> Q2.
> Allegro software will attempt to distribute the serpentine so as to
> minimize the antennae efficiency of the serpentine. If your board
> layout house has Allegro, then specify the required matching paths and
> let the software do most of the work.
>
> When you push all the serpentine turns together, you make a mini,
> phased-array antenna which is not going to make your EMC engineer
> happy. Each of the edges where the serpentine turns can emit pretty
> efficiently.
>
> The degree of coupling on a susceptor trace is the integral of the
> field from the agressor trace(s). In simple terms, the longer a
> parallel route you have between two traces, the greater the coupling.
> So, the answer to c) is really the same as Q1. If you want coupling
> to remain under 10% between different serpentine signals then you need
> to separate by same 3X the height to the reflection plane as you would
> for straight traces.
>
> If you are asking about the coupling between segments of one
> serpentine, the answer is that you do get both some signal degradation
> and increased delay over just the path length due to the coupling
> between opposing segments. How much depends on how long each segment
> is, and how close together you put them. For trace length adjustments
> of a few inches, this is not generally a problem. That is because
> each segment is generally much shorter than 1/2 of the shortest
> wavelength in your signal. If you have a 500pS risetime signal, at
> 200pS / inch, the risetime covers 2.5" of trace. With a maximally
> tight pattern, keep your segments much shorter, so that the coupled
> segments do not cover a significant part of the rise time. The
> alternative is to separate the segments more to weaken the coupling.
>
> You may be able to do better than these estimates, but a more accurate
> answer needs at least a 2D solver. Limited capability solvers such as
> Polar Instruments can be found for as little as \$500 - \$1000. More
> sophisticated product is available from folks like Hyperlynx for
> around \$10,000, or you can mortgage property and buy a complex suite
> from Viewlogic, or InCases, etc. with commensurate training
> requirements.
>
> Regards,
>
> Steve.
> At 11:41 AM 7/20/99 +0800, you wrote:
>
>> I have two questions which I hope you experts out there can
>> enlighten me.
>>
>> Q1 : For years books have indicated that address and data bus must
>> be routed perpendicular to each other on different layers. However,
>> with board getting smaller and high component count, it will be a
>> luxury to do so, isn't it? As such, can I :
>>
>> (a) Route address and data bus side by side on the same layer.
>> (b) If yes, how far apart must the address and data bus be
>> separated.
>> (c) If no, can they be routed parallel to each other on adjacent
>> layer.
>> (d) If no, can they be routed parallel to each other 2 layers away.
>> (e) How much clearance must be there for (b).
>> I would appreciate reasons or explanations be given for the answers
>> to the above questions.
>>
>> Q2 : What is being practice is to route all clock signals with equal
>> length and no via (if possible) on a layer dedicated for them. This
>> is acheived by using those serpentine routing pattern. Can I :
>>
>> (a) Start to introduce the serpentine routing pattern at the
>> outputs.
>> (b) If yes, will there be any coupling between them.
>> (c) If no, how far apart must the next serpentine pattern be formed.
>>
>> _ _ _
>> I I I I I I
>> I I I I I I
>> ______ I I_I I_I I_____
>> _ _ _
>> I I I I I I
>> I I I I I I
>> ______I I_I I_I I_____
>>
>> Hope to hear from anyone of you and thanks in advance.
>> Regards.
>
>
>

--------------FEE29DAC38925F71488282D4
Content-Type: text/html; charset=us-ascii
Content-Transfer-Encoding: 7bit

<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
Thank you very much for being the only repsonse to my questions. I appreciate the answers and clear explanation.

Regards,
Wee Mei

Steve Weir wrote:

Q1.  You need to limit the crosstalk.  Barring purchase of a crosstalk analysis tool, you can estimate the worst case crosstalk as:

CT = 1 / ( 1 + ( x/h )^ 2 ), where x is the center to center distance between parallel traces on the same layer, and h is the distance from the center of the signal etch to the center of the nearest reflection plane, sic where the opposing return current flows.

For example, if you have 5 mils between a given signal layer and the nearest ground plane, then your edge-coupled crosstalk will not get worse than 10% for 15 mil spacing.  Broad-face crosstalk is similar, replacing x with the height between adjacent signal layers.  Assuming that you have packed most traces on 10 mil centers, then you can route one extra phantom trace between the address block, and data block to maintain a total of 20 mils, which will yield x/h of 1/4, or a crosstalk of 1/17, < 6%.  You can use the same technique for clocks, and any other signal which will be used to set timing.

The signals which remain close together may exhibit crosstalk as high as 20% if the traces run parallel for much more than 1/2 wavelength.  This will affect your flight time calculations as adjacent signals which switch to opposing states will take longer to settle.

In crude terms, each line acts as a winding in a pulse transformer both inducing current into the adjacent trace, and receiving current from the adjacent trace.  This reduces the current available to charge the capacitance along the line, increasing the time before the far-end matches the near-end.

If you are pushing frequency limits, you either need decent analysis software, your design will be overly conservative, or your design will be risky.

Q2.
Allegro software will attempt to distribute the serpentine so as to minimize the antennae efficiency of the serpentine.  If your board layout house has Allegro, then specify the required matching paths and let the software do most of the work.

When you push all the serpentine turns together, you make a mini, phased-array antenna which is not going to make your EMC engineer happy.  Each of the edges where the serpentine turns can emit pretty efficiently.

The degree of coupling on a susceptor trace is the integral of the field from the agressor trace(s).  In simple terms, the longer a parallel route you have between two traces, the greater the coupling.  So, the answer to c) is really the same as Q1.  If you want coupling to remain under 10% between different serpentine signals then you need to separate by same 3X the height to the reflection plane as you would for straight traces.

If you are asking about the coupling between segments of one serpentine, the answer is that you do get both some signal degradation and increased delay over just the path length due to the coupling between opposing segments.  How much depends on how long each segment is, and how close together you put them.  For trace length adjustments of a few inches, this is not generally a problem.  That is because each segment is generally much shorter than 1/2 of the shortest wavelength in your signal.  If you have a 500pS risetime signal, at 200pS / inch, the risetime covers 2.5" of trace.  With a maximally tight pattern, keep your segments much shorter, so that the coupled segments do not cover a significant part of the rise time.  The alternative is to separate the segments more to weaken the coupling.

You may be able to do better than these estimates, but a more accurate answer needs at least a 2D solver.  Limited capability solvers such as Polar Instruments can be found for as little as \$500 - \$1000.  More sophisticated product is available from folks like Hyperlynx for around \$10,000, or you can mortgage property and buy a complex suite from Viewlogic, or InCases, etc. with commensurate training requirements.

Regards,

Steve.
At 11:41 AM 7/20/99 +0800, you wrote:

I have two questions which I hope you experts out there can enlighten me.

Q1 : For years books have indicated that address and data bus must be routed perpendicular to each other on different layers. However, with board getting smaller and high component count, it will be a luxury to do so, isn't it? As such, can I :

(a) Route address and data bus side by side on the same layer.
(b) If yes, how far apart must the address and data bus be separated.
(c) If no, can they be routed parallel to each other on adjacent layer.
(d) If no, can they be routed parallel to each other 2 layers away.
(e) How much clearance must be there for (b).
I would appreciate reasons or explanations be given for the answers to the above questions.

Q2 : What is being practice is to route all clock signals with equal length and no via (if possible) on a layer dedicated for them. This is acheived by using those serpentine routing pattern. Can I :

(a) Start to introduce the serpentine routing pattern at the outputs.
(b) If yes, will there be any coupling between them.
(c) If no, how far apart must the next serpentine pattern be formed.
_    _   _
I I  I  I  I I
I I  I  I  I I
______ I I_I  I_I I_____
_    _    _
I  I  I  I  I  I
I  I  I  I  I  I
______I  I_I  I_I  I_____

Hope to hear from anyone of you and thanks in advance.
Regards.

--------------FEE29DAC38925F71488282D4--

**** To unsubscribe from si-list: send e-mail to [email protected] In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****