Re: [SI-LIST] : Via Capacitances ...

bgrossma (bgrossma@td2cad.intel.com)
Fri, 09 Jul 1999 15:48:58 -0700

This is a multi-part message in MIME format.
--------------895282604C912F4B9076FDF6
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Many interesting responses to this topic, some comments of my own:

Mr. Degerstrom makes an excellent point in his closing sentences about
'ratios'. If you take the physical geometry of the via or the parameters
of the pulse to extremes, you will see very different results with a
TDR. Enormous via pads on a very thin substrate will skew the apparent
L:C ratio of the via more towards the C side than say a very small via
pad on a very thick substrate. Other items such as plane clearances, the
existance of pads on different internal layers can all impact the
appearance of a larger C vs. L (or vice versa), I hate to hear global
statments such as all vias appear capacitive or all appear inductive,
swing the boundary conditions to extremes. At DC vias will look neither
inductive or capacitive. For digital or RF signals, try to imagine what
the fields would be doing, would a via continue to look like a
capacitor/inductor at 100GHz?

And my applause to Dr. Sayre's comments which I would paraphrase as
'don't blindly trust your field solver'. There was a story in EDN
recently where a group of design engineers sat around reams of
simulation output that suggested oscillations in a circuit design were
impossible, while FAE's on the other side of the table demonstrated how
the circuit oscillated in nearly every operating condition. I have seen
similar examples (who hasn't?) with blindly trusting the output of a
field solver for something as simple as a via model. The output can be
suprisingly sensitive to the style of launch used, the type of boundary
conditions used, etc. To me it is the equivalent of taking measurements
with uncalibrated equipment.

My $.02 anyway, I don't want to hold up the continuing dialog.

Regards,

-Brett
--------------895282604C912F4B9076FDF6
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Brett Grossman
Content-Disposition: attachment; filename="vcard.vcf"

begin: vcard
fn: Brett Grossman
n: Grossman;Brett
org: Intel Test Tooling Operations
adr: 2200 Mission College Blvd;;MS: SC2-07;Santa Clara;CA;95052-8119;US
email;internet: bgrossma@td2cad.intel.com
title: Sr. Design Engineer
tel;work: (408)-765-2619
tel;fax: (408)-765-2518
x-mozilla-cpt: ;0
x-mozilla-html: TRUE
version: 2.1
end: vcard

--------------895282604C912F4B9076FDF6--

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****