Intel Corporation has immediate openings for CAD/Design Engineers with
Intel Test Tooling Operations in Santa Clara, California. If you are
qualified and interested in applying for this position, or would like to
refer someone who may be, please contact me at:
Primarily responsible for the physical and electrical design of Sort
Interface Unit's (SIU).
The SIU is a passive interconnect between a Si device in its wafer form
and an ATE tester used for the verification of the device prior to being
sliced and packaged. It consists of a Printed Circuit Board (PCB), a
package-like structure, and an array of several thousand probes and is
utilized to deliver 'clean' power and signals while transforming a large
tester geometry (50-100 mil pitch) to a very small device geometry (down
to 10's of microns).
The typical day-to-day activities of the CAD/Design Engineer would be:
o Extracting relevant electrical design requirements from the
upstream customer (Intel product group a.k.a chip DE's)
o Twisting and contortion of these requirements into something
that can actually be realized in the test environment, while
also ensuring that it is manufacturable for use in an HVM factory.
o Specifying the physical design requirements for layout by our
o Reviewing the completed design and associated documentation.
The Engineer would also be responsible for regular development
activities which include:
o Design and layout of PCB/package/Si test structures for
o Measuring and modeling these test structures
o Component characterization/selection
o Performance valuation of next generation materials
o Experience with physical design (PCB, package, VLSI) methods
and tools (Cadence Allegro, APD, Concept, etc.)
o Experience with design for signal/power integrity methods and
CAE/measurement tools (HP MDS/ADS, HFSS, Spice, network analysis,
o Strong communication skills to deal with diverse customer base
o B.S. or M.S. in Electrical or Computer Engineering with 0-4 years
If you or someone you know is interested, please don't hesitate to
Content-Type: text/x-vcard; charset=us-ascii; name="vcard.vcf"
Content-Description: Card for Brett Grossman
Content-Disposition: attachment; filename="vcard.vcf"
fn: Brett Grossman
org: Intel Test Tooling Operations
adr: 2200 Mission College Blvd;;MS: SC2-07;Santa Clara;CA;95052-8119;US
title: Sr. Design Engineer
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