[email protected]
Wed, 21 Jul 1999 14:02:58 -0500


You bring up an interesting question that I have been considering over the
last few days as well. In my case it is SDRAM rather than SSRAM but
the point is the same.

I pulled up the data sheet for the part you are using and I also looked
through several of my data sheets. Unfortunately, the data sheets are
somewhat silent on maximum *AC* operating parameters. As you mention, the
3.6V value is a DC parameter and is not the peak AC voltage the part can

In previous generations many vendors supplied parts that met the PC100
Specification from Intel (for SDRAM that is). If a memory vendor sells you
a part that is PC100 compliant you should be able (note the word should!) to
assume that it meets all aspects of the PC100 Specification. I will leave
the discussion as to whether that assumption is valid for another day.

The PCSDRAM Spec. (Rev. 1.51, pg 45) does have data sheet entries for
"Maximum AC Operating Requirements." The spec is for Vih max = VDDQ+2V and
Vil min = VssQ-2V. Therefore if VDDQ max = 3.6V and VssQ min = 0V. Your
max overshoot would be 5.6V on the positive side and -2.0V on the negative
side. There is also usually a max amount of time the pulse can be at this
voltage. For PC100 parts it is 3ns or less (with no input clamp diodes).

So, when we had this spec we at least had a rough idea of what were
acceptable values. However, I'm now noting that as memory gets faster parts
are no longer "PC100 Compliant" they are now "PC100 Compatible."

Where does that leave us? Are vendors still designing to the PCSDRAM spec?
(as far as things like input capacitance, max operating conditions, etc. go
that is) Can we still assume the above mentioned parameters are valid?

I'm frankly not sure of the answer but this would be a good chance for
anybody at a memory IC house (or any IC house for that matter!) to speak up.

Why do we not see Maximum AC Operating Conditions in current data sheets?


Jim P.

Jim Pankratz
Signal Integrity Group
Dell Computer Corp.
[email protected]

-----Original Message-----
From: JOACHIM MUELLER [mailto:[email protected]]
Sent: Wednesday, July 21, 1999 11:45 AM
To: [email protected]

We find that that with the sub nano second edges on today's drivers,
almost every unterminated signal has an overshoot that exceeds the
maximum voltage rating on the input, if it is more than 1inch away from
the output.

As an example, I am driving with a 500ps edge into a SAMSUNG Memory
KM736V887. The SSRAM is 2 inch away from the driving chip, and my
simulation result shows an overshoot of 4.2V in a point-to-point
topology. Samsung specifies a 'absolute maximum voltage' for this input
of 3.6V.

Would you put a series termination on this net?

Those maximum voltage specs, we find in the data sheets consider a DC
voltage, but what would be the AC margin for this parameter. Of course
it is higher - but how high? Could I consider 2 times the DC maximum
voltage rating for transients as a safe and simple design rule?
I guess the question is, does anybody care about overshoot on
data/address busses before the actual sampling time? If yes, what would
you consider to be an acceptable overshoot?
Our products have to meet long term reliability requirements and I would
think latch up can not be the only failure mechanism to consider.

Any comments would be greatly appreciated


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