Re: [SI-LIST] : Rambus vs. di/dt SSN

Scott McMorrow (scott@vasthorizons.com)
Sun, 25 Jul 1999 18:24:39 -0700

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John,

1) The package is chip scale with extremely low inductance
for the ground pins. Good buffer design, good board power
distribution and good layout will reduce SSO to acceptable levels.

2) The package RLGC is compensated for partially by increasing
the characteristic impedance of the channel in the vicinity of the
package. This compensation presents a uniform loaded channel
impedance of 28 ohms in the 400 MHz region, which is the
standard impedance of the channel in the unloaded regions.
There will be reflections. but only in the higher frequency
harmonics. These, however, are mitigated by items 3 and 4.

3) There is a small input resistance in series with the die
capacitance which helps to reduce the effect of die loading on
high edge rate signals.

4) The channel acts as a low pass filter to propogating waves
due to the distributed capacitance of the devices and the
ac attenuation of the materials (i.e. Skin Effect and Dielectric
Loss.)

The best way to become a believer is to simulate the bus ... assuming
that you have the NDA's in place to correctly model
the drivers.

Regards,

scott

> Hello All SI gurus,
>
> One question about Rambus,
>
> I wonder that the di / dt (current change rate) of rambus is high, how rambus can avoid being attacked by SSN / Ground bounce
> and package noise reflection.
>
> Necking down the trace to compensate rambus chips seems to work in certain level but not tatotally overcome the package's RLCG.
>
> Does somebody have good idea about this?
>
>
> Thanks,
> John Lin
> SI Engineer at Quanta Computer Inc.
> Email: John@quantatw.com
> Tel:(03) 3979000 ext. 5183

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John,

1) The package is chip scale with extremely low inductance
for the ground pins.  Good buffer design, good board power
distribution and good layout will reduce SSO to acceptable levels.

2) The package RLGC is compensated for partially by increasing
the characteristic impedance of the channel in the vicinity of the
package.  This compensation presents a uniform loaded channel
impedance of 28 ohms in the 400 MHz region, which is the
standard impedance of the channel in the unloaded regions.
There will be reflections. but only in the higher frequency
harmonics.  These, however, are mitigated by items 3 and 4.

3) There is a small input resistance in series with the die
capacitance which helps to reduce the effect of die loading on
high edge rate signals.

4) The channel acts as a low pass filter to propogating waves
due to the distributed capacitance of the devices and the
ac attenuation of the materials (i.e. Skin Effect and Dielectric
Loss.)

The best way to become a believer is to simulate the bus ... assuming
that you have the NDA's in place to correctly model
the drivers.

Regards,

scott
 

Hello All SI gurus,

One question about Rambus,

I wonder that the di / dt (current change rate)  of rambus is high, how rambus  can avoid being attacked  by SSN / Ground bounce and package noise reflection.

Necking down the trace to compensate rambus chips seems to work in certain level but not tatotally overcome the package's RLCG.

Does somebody have good idea about this?
 

Thanks,
John Lin
SI Engineer at Quanta Computer Inc.
Email: John@quantatw.com
Tel:(03) 3979000 ext. 5183

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