At the simplest level, board level SI is dominated by capacitance
and inductance while chip level is dominated by capacitance and
resistance onchip and resistance and inductance at the I/O ring.
Because of this, board level designs have far more potential for
self-induced noise (eg reflections and ISI) in contrast to chip
level where crosstalk and SSO effects tend to play a greater
> personally feel that board level SI problems are more prominent as I do
> not have much idea about the chip level SI problems. Also, most articles
> I come across do not seem to address the SI problems at the chip level.
This probably says more about your reading habits than about the
state of the art/industry. Publications tend to specialize along
the lines of their intended readerships, and chip designers are
a different market from PWB designers. Thanks to the overwhelming
complexity of chip-level interconnect, chip-level SI *must* be
addressed at the automated tools level, so the discussions of
on-chip SI are mostly in the CAE fora.
-- D. C. Sessions email@example.com
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