Re: [SI-LIST] : response to semiconductor I/O edge rates

Roy Leventhal (Roy_Leventhal@mw.3com.com)
Fri, 16 Jul 1999 17:11:18 -0500

All,

You guys keep hitting on Texas.

Actually, Fairchild developed the planar process and heavily influence the whole
specsmanship thing. Their ideas included making specs so wide you couldn't
possibly miss and universal devices that would play in any application. Then
crank the diffusion furnaces to just under melting temperature so you could slam
the wafer boats in & out faster.

Shall I go on? I'm getting cranked.

Then the military got into the act (MIL-SPEC) and froze everything at the level
of training and experience, figurativly speaking, of a three year old. Before
long we had a tradition.

Tradition, Tradition.

Regards,

Roy

Scott McMorrow <scott@vasthorizons.com> on 07/16/99 04:09:11 PM

Please respond to si-list@silab.eng.sun.com

Sent by: Scott McMorrow <scott@vasthorizons.com>

To: si-list@silab.eng.sun.com
cc: (Roy Leventhal/MW/US/3Com)
Subject: Re: [SI-LIST] : response to semiconductor I/O edge rates

"Haller, Robert" wrote:

>
> I also agree with D.C. and think we should blow up the ancient carving of
> the 50 pf standard load on that cave wall. :-)
>

I believe the original drawing is in a limestone cave in Texas.

scott :)

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