Re: [SI-LIST] : Slow falling edge of a signal.

Eric Goodill (ericg@cisco.com)
Tue, 09 Mar 1999 22:40:06 -0800

johnlin@ccmail.arima.com.tw wrote:
>
> Dear all SI gurus,
>
> One question.
>
> For a CMOS chip, what will be effects for a slow falling edge ( 2ns from 1.5V to
> 0.8V) of an input?
> Will the chip work abnormally?
>
> Based on its' timing specification , the setup time measurement is to measure
> 1.5V on a clock rising edge to 1.5V on the falling edge of the signal.
>
> Shall it be 1.5V on the clock rising edge to 0.8V of the falling edge of signal
> for the setup time measurement?
> That is because 0.8Volt is a guarantied low state.

If nothing else, a slow edge means the receiver has more trouble placing the
so-called edge in time as compared to a faster edge. If your timing is
extremely tight, then you may want to add some margin for this.

-Eric

-- 
Eric Goodill         Hardware Board Designer     M/S SJ-N2
ericg@cisco.com                                  170 West Tasman Drive
voice: (408) 527-3460                            San Jose, CA 95134
fax:   (408) 527-2324

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