[SI-LIST] : FR-4 and PCB Tolerances

Dave Hoover (dhoover@mccurdy.com)
Fri, 27 Aug 1999 10:23:28 -0700

Patrick wrote:
I always pay a close attention to effects of manufacturing tolerance
variations. SI simulations are carried out for three corners (i.e.
fast, typ and slow), and numerous model and PCB parameters are allowed
to vary according to tolerance requirements. For instance, the value of
substrate dielectric constant may be 4.2 for fast, 4.4 for typical and
4.6 for slow corners. Similarly, substrate thickness for fast, typical
and slow corners can be 5.2 mils, 4.5 mils, and 3.8 mils respectively.
This is considered necessary to verify the design under all conditions.

Experience has proven to me that "stackup extraction", which I had
attempted to explain clearly in my communication, is important. It can
serve to eliminate numerous SI simulation problems and enhance
simulation accuracy.
------------------------------------------------------------------------

Here's my 2 cents on FR-4 variation. See the attached file.
The Er' is a result of the resin to glass ratio. The thinner B-Stage
prepreg has a higher resin content which results with a lower Er'.
However, it would not be in best interests to try and build an .062"
thk PCB out of .002" thick prepregs. Yes, the Er' would be low but the
cost
would be through the roof along with the resin flow out of the
multilayer
press. The dimensional (in)stability could produce misregistered layers.
(Too much movement) As a fabricator, we use the various prepreg styles
to satisfy many things. (Some are.....)
1) To achieve the desired dielectric thickness. (i.e., the thicker plies
may achieve the best cost approach but possibly not supply
sufficient resin to displace the air during pressing. So we would use
two plies rather than single ply.)
2) Meet overall thickness.
3) Meet desired electrical performance requirements. (i.e., Zo, Zdiff,
L, C, Co, Tpd)

FR-4 is (as you know) lossy. So when FR-4 is used at higher
frequencies (e.g. >500 MHz) there is some substantial differences than
the published technical data sheets from the material suppliers that
tested the substrates @ 1 MHz. TDR has a nominal BW at around 1 GHz
(based on FR-4 along with 6" long TDR Coupons) so we (fabricators)
see most modeling programs matching "modeled vs. actual" data with a
Er' at around 10% lower than what's published. (i.e., 4.4 vs. 4.0 Er')

The successful fabricators develop PCB attributes that yield
desired results. These PCB attributes are recorded and stored for future
reference (Empirical data). Sometimes, there is many different ways
to achieve a desired dielectric thickness. Each (prepreg) combination
requires a slightly different linewidth to achieve desired Zo
(due to subtle Er' differences). This includes prepreg resin fill
yield and Er' characteristics from the designed circuitry off the
various innerlayer.

So Pat's comment of:
"I always pay a close attention to effects of manufacturing tolerance
variations.".... is better understood.

The art of PCB manufacturing (as previously stated) definitely
is not an exacting science. However, by monitoring and tracking
the variations encountered with building the PCB, the required
PCB attributes along with the tolerances can be anticipated.

Dave

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