Some logic families (even CMOS ones) have non-symmetric VOH and VOL (TTL 5V
logic with VOH=2.4 and VOL=0.4 is a classic example). In which case, use the
one that gives you the highest noise margin for the non-active signal to
prevent accidental crossings into active mode under SI conditions (e.g. Active
low for 5V TTL). Also, even for centered output VOH and VOL, the input
transition thresholds may not be centered, so watch those noise margins. This
is less of an issue on-chip, where circuits are normally designed with centered
input and output "thresholds".