Re: [SI-LIST] : METASTABILITY IN FLIP FLOPS

Shayle Hirschman (shayle@mho.net)
Wed, 21 Jul 1999 21:39:48 +0000

Thank you Dr. Johnson for an excellent explanation and answer to my
question and to this thread on metastability. Very informative.

It is clear from your explanation regarding the well-damped comparator, the
buffer amplifier, etc., that, as you state, the two-stage (or three-stage)
sampler is superior to the single-stage sampler with a slower clock which I
had always thought was necessary in the past.

I assume that the second flip flop's output is not considered a metastate
signal and therefore can feed multiple flip flops such as usually occurs in
a state machine?

I very much look forward to trying this out at my next high-speed state
machine design opportunity.

Also, Dr. Johson, do you know or does anyone representing a manufacturer
know if the flip flops in FPGAs and PLDs follow this same model and can
also be expected to behave as you have described?

Thanks again for an excellent and useful discussion.

Shayle

*************************************************************
Shayle I. Hirschman, Senior Engineer
Managing Director
Digital Design Solutions
http://www.digital-designs.com
shayle@mho.net
Phone 901/759-1802 Fax 901/759-2324

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