Tue, 27 Jul 1999 13:16:03 -0400

Back in the late 1970's and early 1980's, some IBM component specifications used
to state an MPUL (maximum possible up level) and an MPDL (maximum possible down
level) for overshoot spikes lasting less than a few nanoseconds.

Over my 13 years in Test Engineering and 9 years in Product Development at
IBM/Lexmark, I have personally seen excessive overshoot on falling- and
rising-edges cause the following problems:
* 74LS93 counters counting too fast during In-Circuit Test-- fixed by buffering
the outputs at the bed-of-nails test fixture (documented on
page 33 of my book, "Electronic System Design: Interference and Noise
Control Techniques").
* 74LS96 shift register losing 1's during In-Circuit Test-- fixed by buffering
the outputs at the bed-of-nails test fixture (documented on page
34 of my book, ditto).
* Damage to PAL16L8BCNL PAL's, causing one output pin not to toggle when the
chip got warm.

This last was a real bugger, because just one customer in Europe saw the problem
on our first-generation network adapters that had been in use for three to four
years-- some five years after we had started manufacturing the product! It took
us about three months to find the root cause, because it started as a rare
intermittent failure (once per several months) that gradually got worse (up to
once per week or so) until the customer got fed up and swapped out the adapter.
We finally isolated the problem to certain date codes of die-shrunk PAL's, whose
output pin(s) would degrade from excessive overshoot on falling edges over
several years continuous use when Vcc was close to +5.25V. This showed up as a
voltage/temperature intermittent problem. Even with failure analysis by the
manufacturer of the PAL's, we never figured out the exact damage mechanism. We
wound up replacing several hundred network adapters at that customer with our
latest models for free, in the name of customer good will, at a cost of some
ten's of thousands of dollars to Lexmark and many hours work by my department.

A few months later, early in the development of our fifth generation of network
adapters, we saw serious overshoot on signals going to a synchronous graphics
RAM (SGRAM). Being justifiably paranoid by this time, we immediately contacted
the vendors of the SGRAM's and I searched Lexmark's Technical Library and my
personal library for pertinent information. Cypress, Harris, Logic Devices,
Motorola, National Semiconductor, RCA, Signetics, and Texas Instruments all warn
against input overshoot or input voltages (from power up, power down, or
hot-plugging) that exceed Vdd+0.7V or Vss-0.7V. I also found references to
these additional side-effects from excessive overshoot:
* Latch up of the parasitic SCR formed by the N-channel and P-channel FET's on
the input, destroying the device.
* Interaction with adjacent inputs through parasitic npn/pnp transistors formed
by the input-protection diodes (one of my coworkers saw
this problem in an ASIC that he developed at IBM Boulder).
* Electron injection into the substrate, disturbing internal nodes and causing
soft errors.

In the old 4000-series CMOS, latchup could occur for input currents as low as
10mA. Pulse width and pulse repetition rate, which affect the average input
current, also affect a device's susceptibility to latch-up. Some new devices
are designed to have latchup currents exceeding 1A through the use of:
* Substrate biasing.
* Substrate type.
* Substrate resistivity.
* Epitaxial layers.
* Well conductivity.
* Well depth.
* Taps to the substrate.
* Guard rings.
* Spacings.
* Metal straps to sensitive areas.
* Series input resistance.
* Other layout tricks.

As a board designer, I do not have much clout with the chip designers. Even if
I did they are constrained by the technology they want to use for many other
reasons. In many cases I am forced to use a particular chip because it is the
only one that will provide the functions I need for a reasonable cost. Thus
series-termination at the source has been my major weapon against overshoot on
signals for our last three generations of network adapters. I insist that we
look at every signal on a new board with a fast oscilloscope very early in
product development, and that we recheck any areas where we change parts or the
board layout after every change. We have had very good results using series
resistors that are a little higher than would be required to perfectly match the
IC's output impedance to the trace impedance. This trades off a
slightly-overdamped signal and the resulting decrease in the edge rate for a
little more margin in production, since we can not guarantee that the IC
manufacturer won't decrease the output impedance over the production-life of our
product. We do verify that any "stair-stepping" we introduce by the
higher-valued series resistors is well under Vil or well over Vih, so we don't
cause ourselves yet another set of problems.
John Barnes
Advisory Engineer

**** To unsubscribe from si-list: send e-mail to In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at ****