Regards,
At 09:20 AM 6/14/1999 -0400, you wrote:
>Steve,
>I agree except for your statement about capacitance being inversely
>proportional to the plane separation. In fact, the capacitance of a
>parallel plate capacitor is proportional to A/d (A=area of plates,
>d=separation). The energy storage, on the other hand is E=(1/2)*C*V^2,
>which is proportional to 1/d^2.
>Eric Sweetman
>
>> ----------
>> From: Steve Weir[SMTP:[email protected]]
>> Reply To: [email protected]
>> Sent: Friday, June 11, 1999 5:05 PM
>> To: [email protected]
>> Subject: Re: [SI-LIST] : How do you use buried capacitance?
>>
>> Chris,
>>
>> The theory is pretty straightforward, this is just a parallel plate
>> capacitor. The thrill is that Zycon offers a fairly thin dielectric, so
>> the capacitance is much better than what is possible with typical
>> fiberglass. For 10mil separation between planes, the approximate
>> capacitance is 100pF per square inch. With Zycon, the separation is
>> 2mils,
>> so we get 25X the capacitance per square inch = 2.5nF/"^2. Because this
>> is
>> a plate capacitor, it has very high bandwidth. Because it is distributed
>> across the PWB assembly, we get very good load sharing. This also helps
>> the return current coupling as the signal trace moves from one plane to
>> another.
>>
>> You will still need to use bulk capacitors for mid-frequency decoupling,
>> ie
>> some number of 100nF, and multi-microfarad caps.
>>
>> Regards
>> At 10:17 AM 6/11/99 -0700, you wrote:
>> >I understand the priciples behind buried capacitance. What I don't
>> >understand is how you use it when designing a board.
>> >
>> >Is it only used for decoupling?
>> >
>> >How do you figure out how much decoupling capacitance it is equivalent to
>> >for a particular IC?
>> >
>> >Do you use it along with your standard decoupling capacitors (for added
>> >effect)?
>> >
>> >Thanks,
>> >
>> >Chris
>> >
>> >
>> >
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>>
>>
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>
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