1. Yes, there is a noise ceiling. However, the value depends on what
familie(s) of logic are on the board. The relative potential at the ground
reference of the receiver versus the transmitter directly subtracts from
the noise margin of the receiver. This includes not only the ground plane,
but the interconnect of both the transmitter and receiver. This is one
reason this thread has been so full of discussion over edge rates lately.
2. If your care to spend a lot of money, Viewlogic offers a product called
AC-GRADE for evaluating plane potential distribution.
3. It is definitely part of both the signal and emitted noise budgets. How
you perform your layout planning and evaluation is an internal process
4. Qualitatively, EMI will increase with the plane noise in your system.
However, it is the area loops which do the damage with the magnetic field.
So, if you are looking for a formula for a hand calculator, I can't help.
A small current with a large loop antenna is going to hurt as bad or worse
then a very large current in a well confined loop.
At 01:03 PM 7/26/1999 -0400, you wrote:
>I'm looking to correlate PCB ground noise voltage to an EMI levels.
>My understanding goes as far as: the voltage is measured from the PCB ground
>input to a point on the board differentially. That voltage drop is the
>noise voltage. The voltage drop tells us that there is common mode
>current. If we knew the impedance between the two points we could then
>calculate the common mode current.
>Since every PCB and has different geometry's and cables (power and I/O), the
>difficult unknown is the impedance.
>Is there is an absolute noise voltage level that should never be exceeded?
>Is there a way to "accurately" quantify the impedance's of the PCB ground
>plane and cables?
>Can noise voltage become a PCB design specification?
>Most importantly, when all is said and done, is there an "accurate"
>correlation between noise voltage and EMI levels?
>Thanks for the input
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