Actually, the first order effect on the amount of jitter comes from the type
and speed of the circuit used to generate or transmit the clock or data.
High speed ECL or PECL will have the lowest jitter followed by high speed
analog CMOS followed by high speed bipolar saturated logic and the highest
jitter would be from high speed digital CMOS logic. All else being equal, of
course, and ignoring power versus performance issues.
Your suggestion will give Shubin a simulation of the power supply sensitivity
and single and common mode power rejection of his design if he is using a
clean input clock or data. Shubin would do well to also examine the source,
type and amount of his input jitter as well as the input rise time and errors
in the threshold trigger point.
If you want an interesting experiment, try building a PLL circuit around the
4046, 7046 and 9046 series of phase lock loops with a single socket and power
supply and plug in each and measure the jitter. Same power but different
technology and much different jitter output. (9046 is the best)
Physicist & Consultant
Begin Included Message:
> Harold Snyder wrote (in part);
> > Shubin,
> > Once you have converted to ECL or PECL
> > your noise should not get worse than it was at the input to the 100ELT22
> > unless you have noise on your power lines.
> From: firstname.lastname@example.org (Stephen Peters):
> From my understanding, most PLL jitter comes from power and ground noise.
> Instead of connecting a perfect voltage source to the VCC lead, should
> probably carefully model the power delivery and ground return paths to/from
> the part and inject a little random noise into the voltage source.
End Included Message.
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