Re: [SI-LIST] : RE: Another decoupling question

Per Torstein =?iso-8859-1?Q?R=F8ine?= (perr@ifi.uio.no)
20 Sep 1999 20:00:23 +0200

"D. C. Sessions" <dc.sessions@vlsi.com> writes:
> > I agree the best capacitance is on-die. It is expensive in die area, but
> > becoming more and more essential as edge rates and speeds increase.
> > However, there exist devices already without such provisions and I was still
> > wondering whether capacitors can be placed under BGA packages to help
> > existing power decoupling problems. Is it cost effective and
> > manufacturable?
>
> On-chip decoupling isn't so much expensive in die area (because die
> area is generally interconnect-dominated) but it does impact on yield
> because of the increase in gate-oxide area where a gate failure can
> cause a supply short.

This reminds me of an article I saw once about a fast IBM CMOS
processor that had on-chip decoupling capacitors (I don't remember any
specifics). If I recall correctly, the capacitors were made from large
square poly-diffusion thinox areas with diffusion contacts around the
edges, and with a minimum-with poly connection from each thinox poly
square to Vdd. If there was a short in the oxide, the narrow poly
connection would blow like a fuse and deconnect that decoupling
capacitor.

I think the series resistance with this layout means that the
decoupling capacitor is almost useless above maybe some hundred MHz.
If I am correct, on-chip decoupling is mostly useful at very high
frequencies (above the clock frequency) in order to reduce di/dt of
the supply wiring/pads. My idea of on-chip decoupling capacitor looks
like some kind of Scottish pattern:

D P D P D P
| | | | | | | | | | | |
+ +-+ +-+ +-+ +-+ +-+ +-
X | | X | | X | | Diffusion
+ +-+ +-+ +-+ +-+ +-+ +-
| | | | | | | | | | | |
+-+-+ +-+-+-+ +-+-+-+ +-
X X X Poly
+-+-+ +-+-+-+ +-+-+-+ +-
| | | | | | | | | | | |
+ +-+ +-+ +-+ +-+ +-+ +-
X | | X | | X | | Diffusion
+ +-+ +-+ +-+ +-+ +-+ +-
| | | | | | | | | | | |
+-+-+ +-+-+-+ +-+-+-+ +-
X X X Poly
+-+-+ +-+-+-+ +-+-+-+ +-
| | | | | | | | | | | |
D P D P D P

The capacitance per area is of course lower than for a large thinox
area, but the series resistance is also much lower. I assume that both
structures use poly over N+ in N-well. Do you think this technique is
worthwhile, or is the series resistance not that critical?

-- 
Per Torstein Roeine                            email: perr@ifi.uio.no
University of Oslo                             phone: +47 22 85 24 52
Dept. of Informatics, Microelectronics Group     fax: +47 22 85 24 01
Box 1080 Blindern, N-0316 OSLO, NORWAY

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