Re: [SI-LIST] : Package Parasitics Modelling

Lynne Green (green@wolfenet.com)
Mon, 29 Mar 1999 17:09:45 -0800 (PST)

10K protection??? Many of the 0.25um-and-under processes get 1K to 4K.

Watch your library suppliers (in-house or custom). Some say "designed to xK"
but do not tell you what they actually achieve. Sometimes, the first ESD
results come from customers (i.e. you!), not their own tests. (This is for two
reasons: 1. They don't do test wafers on every process and every I/O cell, and
2. Designers want to use the libraries today, not wait 3-6 months for ESD
results.)

Also re edge rates: some interface specifications include edge rate
requirements (such as PCI 3.3V, which is 1-4 V/nsec). Edge rates are often
limited at the I/O to reduce ringing amplitudes and improve settling time.
This is an old trick borrowed from telegraph and telephony technology.

Lynne Green
Signal integrity engineer (available for hire, thanks to Duet Technologies!)
resume available on request.

On 29-Mar-99 Christian S. Rode wrote:
> Still, 3 ohms (?) is much better than 0.05 ohms. I guess I wrote that
> last message from an obsolete perspective. In days gone by I think
> they intentionally used to add a poly serpentine resistor (over thick
> field oxide) to limit the discharged current. How they get to 10KV
> input protection today is beyond my ken.
>
> A modern model might then be 3 ohms in series with
> protection diode capacitance + 100 ohms (several squares of
> 20 ohm /sq diffusion/poly) in series with the input gate capacitance
> (negligible?)
>
> tomda wrote:
>
>> If there was significant resistance between the input pin and the C
>> associated with the input protection devices it would show up in the input
>> VI curves. We don't see any significant R in series with the protection
>> devices when we make our measurement based models. The current in those
>> "diodes" can easily get to over 100 mA before the voltage across the device
>> is 1 volt.
>>
>> Tom Dagostino
>>
>> -----Original Message-----
>> From: Christian S. Rode [SMTP:csrode@mediaone.net]
>> Sent: Monday, March 29, 1999 11:16 AM
>> To: si-list@silab.eng.sun.com
>> Subject: Re: [SI-LIST] : Package Parasitics Modelling
>>
>> A question about IBIS input models. I assume a good portion of the input
>> capacitance
>> of these models (C_comp) is associated with the input protection structures
>> and that
>> there can be significant resistance between that capacitance and the pad.
>> That's
>> not modeled in (earlier) IBIS models (and the EIA FAQ's "it's included
>> in the I-V characteristics" isn't relevant). 50 milliohms (or whatever)
>> for R_pkg will
>> give an unnaturally high-Q for the input model. What would be a range of
>> numbers for
>> R between the L and C? (I'm currently guessing 100 ohms)
>>
>> Chris Rode
>>
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----------------------------------
E-Mail: Lynne Green <green@wolfenet.com>
Date: 29-Mar-99
Time: 16:58:12

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