RE: [SI-LIST] : The overshoot and undershoot criteria in PCI spe

Volk, Andrew M (andrew.m.volk@intel.com)
Tue, 12 Oct 1999 08:02:25 -0700

John -

Those are just the overstress test conditions. The voltages are the
overshoot seen at the open end of a transmission line after a step equal to
approximately the power supply. The wave doubles and reflects back on the
receivers. Note that there is a resistor in series with that voltage that
represents the lowest value of trace impedance that might be seen from a
reflected wave. This is just a test setup to test I/O robustness. The
voltage at the pin will be much less. For this reason, it is important that
you meet the clamping specs also listed in the PCI spec.

Andrew Volk
Intel Corp.

-----Original Message-----
From: John@quantatw.com [mailto:John@quantatw.com]
Sent: Tuesday, October 12, 1999 1:35 AM
To: 'si-list@silab.eng.sun.com'
Subject: [SI-LIST] : The overshoot and undershoot criteria in PCI spec.

Dear all SI Experts,

What are the overshoot and undershoot criteria for PCI 5V and 3.3V
environment?
Based on PCI spec. rev. 2.2, 4.2.2.3 Section, Maximum AC Ratings and Device
Protection,
for 3.3V PCI, the criteria seems to be 7.1V for overshoot and -3.5V for
undershoot.

For 5V PCI, 11V is for overshoot and -5.5V is for undershoot.

I wonder that such big overshoot and undershoot voltages will affect the
reliability of chips even the voltages are within the spec.

Your comments are appreciated.

Best Regards,
John Lin
SI Engineer
Quanta Computer Inc.


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