Re: [SI-LIST] : Call for presentations, 3-D packaging advanced technology workshop

Gregg Fokken (fokken.gregg@mayo.edu)
Wed, 21 Jul 1999 08:12:56 -0500

On Jul 20, 3:32pm, Lyke James Civ AFRL/VSSE wrote:
> Subject: [SI-LIST] : Call for presentations, 3-D packaging advanced
techno
> Is anyone out there interested in giving a talk to the 3-D packaging
> community on the signal integrity implications of 3-D packaging, or
future
> trends in signal integrity that could impact 3-D packaging? The workshop
> is in Chicago, Monday 25 October. I have conducted an Advanced Technology
> Workshop for the International Microelectronics and Packaging Society
> (IMAPS) for the last four years on 3-D, and I never have really got a
good
> discussion on this topic.
>
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>-- End of excerpt from Lyke James Civ AFRL/VSSE

Lyke,

I can't make your workshop, but wanted to share some limited experience
we've had with 3-D packaging and would be curious to hear yours or others
feedback or comments.

A while back we were tasked to model a bus which originated on a flex
circuit, attached to the side of a "cube" of stacked die. The bus was then
routed along the edge of the cube (orthogonal to the transistor layer of
each die) with *many* bus drops into the edges of the stacked die. There
were dozens of die with all I/O brought to one edge where they connected to
our bus.

Two problems seemed to stand out. The first was that the input circuits on
the bare die (there were many per bus trace) had a lot of capacitance in
the ESD protection circuitry (can't elaborate). Since the die were very
close together (~30 mils for unthinned die, much less for thinned die), the
capacitances acted as distributed rather than lumped elements and tended to
greatly lower the impedance of our interconnect. It seemed that ASICs
designed specifically for this cube should have had ESD protection designed
for the "cube as a whole" rather than each die. Has anyone seen this
problem, and if so, how did you deal with it?

Secondly, it was difficult to figure out how to model the ground return
path. The manufacturer wouldn't or couldn't put enough layers on the edge
of the cube for us to have a ground plane for our bus signals. Normally
you could view the doped silicon as ground, however, we were crossing over
the "edges" of many silicon die which didn't have their substrates
electrically connected in a direct manner. In our analysis, we finally
made some assumptions about the inductance associated with the ground
return, but were never able to verify against measurements. :-( This
project is over, but it always bugged me that I never knew for sure how the
measured results would have looked. Has anyone out there done this time of
thing and seen measured results? Thanks in advance for any feedback.

-- 
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Gregg Fokken                Internet(email):  fokken.gregg@mayo.edu
Mayo Foundation                       Phone:  (507) 284-5692
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Rochester, MN  55905  

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