Re: [SI-LIST] : Ground gap problem

Fred Balistreri (fred@apsimtech.com)
Tue, 04 May 1999 08:53:23 -0700

Mike Hughes wrote:
>
> I am also interested in Rajkumar's question. Mainly the "why" part of it.
>
> If an IC's power and ground pins are connected to planes there are 3 ways to
> connect a decoupling cap:
>
> 1. connect a cap directly to the planes (using via's) in the vicinity of the IC
> (without connecting to the IC).
This works well when the caps are very close to the IC pins to be
decouped and the application is strickly digital. If there is
sensitive analog nearby and its sharing gnd planes this may not be
the ideal way.
>
> 2. connect a cap to the IC power and ground pins (using traces) without
> connecting the cap to the planes.
Not a good idea for digital applications. The proximity to the pins
and trace width used can kill you. Yes I mean inductance.
>
> 3. connect a cap to the IC power and ground pins (using traces) AND connect the
> cap to the planes (using via's).
The high speed current will take the path of least inductance. The
traces may not buy you anything. A simulation of this case would be
needed to study the effects. One of the concerns here may be EMI.
>
> The cap should be as close as possible to the power and ground pins to lower
> inductance. #3 doesn't seem to be a good idea because of ground loops(?) The
> only difference between #1 and #2 seems to be the inductance. Could it be that
> using #1 and #2 doesn't matter as long as you get the lowest possible
> inductance?
Unless its a rather long and skinny via the planes method would provide
the
lowest inductance path. However each design is different and it would be
wise to
model such effects. The IC package may also greatly influence which
method can
or cannot be used and its effectiveness.

Best Regards,

>
> Sorry if this is an old question.
>
> Thanks,
> Mike
>
> > -----Original Message-----
> > From: Rajkumar C [mailto:craj@india.ti.com]
> > Sent: Monday, April 26, 1999 12:11 PM
> > To: si-list@silab.eng.sun.com
> > Subject: RE: [SI-LIST] : Ground gap problem
> >
> > Hi guys,
> >
> > I have a very basic question.
> > Generally, there is a guideline that every
> > IC's used in the PCB should have a decoupling
> > capacitor near the power and ground pins.
> > Here is my question:
> > In the PCB, I have a separate power plane and
> > ground plane. For all the IC's I am using the Decoupling
> > capacitors.
> >
> > * connect the power and ground pins to the Decoupling
> > capacitors first and then connect the capacitors to Planes
> > (or)
> > * Connect the Power and ground pin to the plane directly and
> > have decoupling capacitors connected to power and ground plane
> > and also placed near the IC's power supply pin.
> >
> > In the above two methods which is best and why?
> >
> > Expecting your answers.
> >
> > Thanks and regards,
> > Rajkumar.
> >
> > **** To unsubscribe from si-list: send e-mail to
> > majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE
> > si-list, for more help, put HELP. si-list archives are accessible at
> > http://www.qsl.net/wb6tpu/si-list ****
> >
> > **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at
>
> --
> ================================
> Mike Hughes
> Product/Test Engineer
> High Speed Conversion
> Analog Devices, Inc.
>
> Phone 781-937-2370
> Fax 781-937-1011
> mailto:mike.hughes@analog.com
> http://www.analog.com
> ================================
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at

-- 
Fred Balistreri
fred@apsimtech.com

http://www.apsimtech.com

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****