RE: [SI-LIST] : Automatic/Semi-automatic design check of PCB layo

Knighten, Jim L (JK100005@exchange.SanDiegoCA.NCR.COM)
Thu, 2 Sep 1999 12:35:54 -0700

Ron,

Check out the following web site from University of Missouri-Rolla.

http://www.emclab.umr.edu/consortium/
<http://www.emclab.umr.edu/consortium/>

They have sponsored an industry consortium over the past 3 years developing
EMI Expert System algorithms that are intended to do just what you ask.

Some of their software partners have products out that implement these
algorithms.

Good Luck,

Jim
________________________________________________________
Dr. Jim Knighten e-mail: Jim.Knighten@SanDiegoCA.NCR.com
<mailto:Jim.Knighten@SanDiego.NCR.com>
Senior Consulting Engineer
NCR
17095 Via del Campo
San Diego, CA 92127 http://www.ncr.com <http://www.ncr.com>
Tel: 858-485-2537
Fax: 858-485-3788

***** Notice the Area Code change from 619 *****

-----Original Message-----
From: Ron Miller [mailto:rmiller@Brocade.COM]
Sent: Thursday, September 02, 1999 10:18 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Automatic/Semi-automatic design
check of PCB layout database for crosstalk/SI violations.

Hi Guys

What technique or tools are being used for checking a new
PCB layout database for simple
mistakes, like excess crosstalk or "BIG" impedance
mismatches before releasing a PCB
for FAB.

My focus is the housekeeping signals and lower speed busses,
that we usually neglect but which
can still bite us in the posterior, causing a new spin of
artwork and FAB.

Requirements in order of importance:
1. Compatibility with PCB databases like Allegro/Cadence
2. Simple to use, little or no training
3. Cost of acquiring
4. Speed of processing

If there is not such a product someone needs to get busy.

Ron Miller

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