RE: [SI-LIST] : Edge Rates

Abe Riazi (ariazi@anigma.com)
Thu, 8 Jul 1999 15:14:26 -0700

Hi Ken:

The following table, which illustrates typical values for several
different technologies of logic families, may be of interest to you:

Advanced Schottky, Tr = 1.9 ns, Pd = 0.17 ns/in, Lc = 5.59 in;

BiCMOS, Tr = 0.7 ns, Pd = 0.17 ns/in, Lc = 2.06 in;

ECL, Tr = 0.5 ns, Pd = 0.17 ns/in, Lc = 1.47 in;

GaAs, Tr = 0.3 ns, Pd = 0.17 ns/in, Lc = 0.88 in;

Where, Tr represents the rise (or fall) time, Pd the propagation
delay, and Lc is the critical line length (i.e. minimum trace length
susceptible to signal distortion).

Above values were obtained from:

Saal, F. "Modeling and simulation Capabilities smooth signal-integrity
problems", EDN, Dec. 7, 1995, PP. 141-150.

Regards,

Abe Riazi
ariazi@anigma.com

>----------
>From: Ken Patterson[SMTP:ken.patterson@pathway-inc.com]
>Sent: Thursday, July 08, 1999 12:06 PM
>To: si-list@silab.eng.sun.com
>Subject: [SI-LIST] : Edge Rates
>
>I am a newcomer to signal integrity analysis and would like to know how
>to find out what the typical edge rates (i.e. rise and fall times) of
>some of the industry standard logic families are. These include FCT
>logic, SDRAMs and Syncburst SRAMs . I have an upcoming project that
>will use these devices and would loike to perform some signal integrity
>analysis.
>
>Ken Patterson
>Electronic Engineer
>ADC Broadband Communications/Pathway Division
>email:ken.patterson@pathway-inc.com
>
>
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