Re: [SI-LIST] : Q: Plane-jumping return currents

Larry Smith ([email protected])
Wed, 22 Sep 1999 14:10:31 -0700 (PDT)

Leesa - All of your comments are correct and you are asking a very good
question. This is a common stackup for our systems and a good one.
The power planes are well decoupled (or well coupled is probably a
better way to state it).

The short answer is yes, there should many vias connecting the ground
layers. At one time I used to tell designers to make sure that every
square inch of PCB had a via connecting the ground planes. That was
close enough for energy to make it from the signal via to the ground
via and back several times durring the signal rise time. Edges will be
well preserved. But as we go to 150 pSec rise times, perhaps a via
every square cm is in order.

If vdd1 and vdd2 are the same voltage, then via them together also. If
they are not the same voltage, we still have a good path through the
thin dielectrics and the well connected ground planes.

The stackup that you have shown is often repeated several times
vertically. It is possible for signals to be referenced against any
plane, hit a via, then end up referenced to any other plane. As long
as every power plane is closely coupled to a ground plane and all the
ground planes are connected often, we have a good return path.


> Date: Wed, 22 Sep 1999 13:47:14 -0700 (PDT)
> From: Leesa Noujeim <[email protected]>
> Subject: Re: [SI-LIST] : Q: Plane-jumping return currents
> To: [email protected]
> Cc: [email protected], [email protected]
> MIME-Version: 1.0
> Content-MD5: 9uA0UeE5GoaHoh92rH+UPw==
> Hi Larry -
> I read with interest your response on the plane-jumping
> question. It brought to mind something I have been wondering
> about for a while. Say we have an imaginary stackup similar to
> Eric's Stackup 2, but with two extra planes. Note that
> planes vdd1 and vdd2 are the same rail, and are tied together
> everywhere a vdd via is dropped.
> via
> >> vdd1 =========== | | ==========
> >> gnd1 =========== | | ==========
> >> trace A ------------| |
> >> trace B | |-----------
> >> vdd2 =========== | | ==========
> >> gnd2 =========== | | ==========
> Now I have good high frequency decoupling between vdd1-gnd1
> and vdd2-gnd2. Let's neglect the interplane decoupling
> between gnd1 and vdd2 - presume our dielectrics are thick
> enough that this capacitance is ineffective. This lets us
> focus on the plane sandwiches (buried capacitance layers,
> power-gnd sandwiches: is there a commonly used term for this
> structure?).
> Although I have a good path from vdd1 to gnd1 and from
> vdd2 to gnd2, I do not have a good path from gnd1
> to vdd2 (i.e. the path which the "return current" would like
> to follow) unless I have a via nearby which connects either
> vdd1-vdd2 or gnd1-gnd2. The return current still needs to
> flow out to the nearest via. Presumably if I am routing
> near a component, I should have lots of power and ground
> vias; it is, however, conceivable that my signal via
> could be an inch or more away from the nearest power or
> ground via.
> Larry, does what I'm talking about above make sense? Do you
> think it is worthwhile to have a regular grid of power/gnd
> vias? Do you know if we have an inhouse tool that could
> evaluate a .brd file from Allegro for the proximity of
> each signal via to an appropriate return via?
> Your comments are much appreciated!
> Regards,
> Leesa