You have made an excellent point! One has to be careful that when
the differential IBIS model is translated into the native model format
of the simulator, the launch skew is not lost (it may require manual
incorporation). One interesting observation that I have made when
simulating (using XNS) differential models is that the nets associated
with both the inverting and non-inverting pins are displayed as a
"single net" waveform, which is very useful and allows evaluation of
In my original post (Distinguishing Differential Models), there were
few typographic errors that I recognized only after having sent the
email. Although minor, let me take this opportunity to correct them.
The name of the buffers in the IBIS model for both of the complementary
pins should have been identical, namely "outbufb". The XTK models
should have also displayed the same buffer model name, as corrected
PIN 18 TYPE outbufb 20 NEG L=1.6 C=0.3
PIN 20 TYPE outbufb 18 POS L=1.6 C=0.3
(With [Diff Pin] present in the IBIS model), and
PIN 18 TYPE outbufb L=1.6 C=0.3
PIN 20 TYPE outbufb L=1.6 C=0.3
(When [Diff Pin] section removed from the IBIS model)
As emphasized in previous occasions, the driver models must be
calibrated for purpose of timing synchronization and this also applies
to differential drivers.
>From: Scott McMorrow[SMTP:email@example.com]
>Sent: Saturday, September 25, 1999 9:50 AM
>Subject: Re: [SI-LIST] : Distinguishing Differential Models
>It should be pointed out that the differential pin launch skew constitutes
>a common mode signal on the differential pair net. No matter
>what we do at the board and system level, we cannot get away
>from the fact that there is still a common mode component
>in all differential transmission. It may be small, but it cannot
>be completely ignored.
>In the particular case of yours the launch skew, or asymmetry,
>is 55ps. Depending on the driver edge rate, this will cause
>a significant common mode signal. If the signal swing were
>1 volt in 550ps, then there would be a 100 mV common mode
>signal component transmitted along with the differential
>signal. Any point in the system open to emission would then
>radiate big time.
>Ideal differential signals do not cause significant radiated
>emissions. "Real" differential signals do depending on
>SiQual, Signal Quality Engineering
>18735 SW Boones Ferry Road
>Tualatin, OR 97062-3090
>Abe Riazi wrote:
>> Dear All:
>> The archives of this forum contains a significant amount of
>> information regarding differential signals. Numerous authors have
>> discussed various key characteristics of differential transmission lines
>> such as impedance of differential pairs and single-ended lines as a
>> function of odd and even mode impedance, broadside coupling vs. edge
>> coupling, equal trace length vs. constant trace separation, return path
>> current distribution, termination, common-mode (CMM) noise,
>> measurements, etc. However, very little has been written about
>> differential models. Actually these models possess some unique features
>> well worthy of consideration.
>> Let us explore differential models by means of a simple example.
>> Presented below is a part (which includes only the differential pairs)
>> belonging to the [Pin] and [Diff Pin ] sections of IBIS model of a
>> differential clock generator:
>> [Pin] signal name model_name
>> R_pin L_pin C_pin
>> . . .
>> . . .
>> . . .
>> . . .
>> . . .
>> . . .
>> 18 CLKB outbufb
>> 20.0 m 1.60 nH 0.3 pF
>> 20 CLK outbuffb
>> 20.0 m 1.60 nH 0.3 pF
>> [Diff Pin] inv_pin vdiff
>> tdelay_typ tdelay_min tdelay_max
>> 20 18 0.00 V
>> 0.00 S -55.0 pS +55 pS
>> The [Diff Pin] section above is the complete section of the model.
>> However, the [Pin] section includes only those pins associated with the
>> differential pair, and the remaining pins have been omitted.
>> The IBIS keyword [Diff Pin] can be utilized to relate differential
>> pins, differential threshold voltages and timing delays. The first
>> column (i.e. [Diff Pin] ) represents the non-inverting pin name. The
>> second column (i.e. inv_pin ) corresponds to the inverting pin name
>> for the I/O buffer. It is necessary for each pin name to match the pin
>> names listed in the [Pin] section of the model. The third column (i.e.
>> vdiff ) presents the output and differential threshold voltage between
>> pins (provided they are Input or I/O pin types). The typical, Minimum
>> and Maximum launch delays (of non-inverting pins relative to inverting
>> pins) are given by the fourth, fifth and sixth columns respectively.
>> Before utilizing an IBIS model in a simulation, it is frequently
>> required to translate the IBIS file into the native model format of the
>> simulator. Usually, the translated models also identify the
>> differential pins by means of polarity indicators. For example, the
>> differential pins of XTK models of above example include POS and NEG as
>> illustrated below:
>> PIN 18 TYPE outbuff 20 NEG L=1.6 C=0.3
>> PIN 20 TYPE outbuff 18 POS L=1.6 C=0.3
>> All of the differential IBIS models that I have worked with included
>> the [Diff Pin] section. However, it is possible for a differential
>> model to be missing this section. This is especially true because based
>> on IBIS specifications the [Diff Pin] section is not a requirement. I
>> have investigated this possibility by removing the [Diff Pin] section,
>> translating the model to Quad, then testing it in a simulation. The
>> converted models now lacked polarity indicators (as expected), that is:
>> PIN 18 TYPE outbuff 20 L=1.6 C=0.3
>> PIN 20 TYPE outbuff 18 L=1.6 C=0.3
>> and caused erroneous simulation.
>> In summary, a differential IBIS model (driver or receiver) can be
>> distinguished by presence of a [Diff Pin] section which follows the pin
>> mapping part. According to IBIS specs, [Diff Pin] keyword is not a
>> requirement, but its absence (in a differential IBIS model) can lead to
>> errors during the translation and simulation stages.
>> Your comments are much appreciated, and I feel obligated to thank
>> Walt Otto, Dale Terrien and John Yuratovac for having expertly
>> described to me many interesting concepts related to differential pairs
>> and signal integrity.
>> Best Regards,
>> Abe Riazi
>> SI Engineer
>> Anigma, Inc.
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