[SI-LIST] : Looking inside the IBIS model

Todd Westerhoff (toddw@cadence.com)
Thu, 27 May 1999 00:12:55 -0400

Hi all (again),

I fixed the presentation on buffer delay and clock cycle budgeting so that it now includes the notes text, and posted a new copy at:

ftp://ftp.cadence.com/pub/timing101a.zip

for those of your who may care to download it and read it. You comments and suggestions for improvements are appreciated, which I will incorporate as time permits.

Todd.

<excerpt><bold>

</bold></excerpt> <bold>Todd Westerhoff

</bold><color><param>0000,0000,ffff</param> Technical Marketing
Director | High Speed Systems Design | Performance Engineering

</color><color><param>ffff,0000,0000</param> Cadence Design Systems |
270 Billerica Road | Chelmsford, MA 01824

</color>

ph: (978) 262-6327

fx: (978) 446-6798

email: toddw@cadence.com

internal information website: http://www-ma.cadence.com/~toddw

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