[SI-LIST] : Trace Impedance vs Supply Noise

Robert Lindsell ([email protected])
Mon, 13 Sep 1999 11:26:32 +1000


I'm designing a test board for an ASIC we are developing here. My
immediate dilemma is determining how much high frequency decoupling to

I've seen various methods to calculate this, usually based on three

1. Delta_v - Maximum allowable voltage droop.
2. Delta_i - Maximum current drawn during switching of synchronous
3. Delta_t - 20% to 80% Rise/Fall time of outputs

Given these you can calculate the required source impedance of the board
power supply;

X_board = Delta_V / Delta_i

Delta_t can be used to estimate the frequency where most of the energy
of the transient is concentrated;

F_high = 0.5/Delta_t

At the highest frequencies PCB interplane capacitance will provide some
useful decoupling, whereas the decoupling capacitors are less useful due
to self inductance, so you need more of them to achieve a sufficiently
low impedance.

If I use these methods, eventually I get a figure for the number of
decoupling capacitors, in this case a disturbingly high figure!

It seemed to me that I could reduce this figure by reducing the
transient current at each output by increasing the impedance of the
traces. Simulation seemed to confirm this too.

My questions are;

1. What factors determine what constitutes a "good" trace impedance for
a given application?

2. A typical value I've seen for high speed traces is 50 Ohms... but

3. PCI traces are specified to be between 60 and 100 Ohms, what
advantage is there to using a higher impedance in this case?

One difference I noticed in my simulations was that for the lower
impedance traces, when using series termination, the requirement to
match the output impedance of the buffer to the trace using the series
terminator meant that the effective source impedance was lower, so any
reflections were damped out more quickly. Could this be one of the
reasons high speed traces are usually 50 Ohms?

Using higher impedances than 50 Ohms seems attractive, but I suspect
there are some disadvantages that I haven't thought of. Can anyone
enlighten me please?

Many Thanks, Robert

Robert Lindsell, Senior Hardware Engineer   |
[email protected]
Canon Information Systems Research Australia| Phone: +61-2-9805-2876
PO Box 313 NORTH RYDE NSW 2113              | Fax:   +61-2-9805-2929

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