[SI-LIST] : [SI-LIST]:Drivers to minimize reflections
Bobby Hubertus (BobbyH@BBSTelecom.com)
Wed, 8 Sep 1999 12:41:49 -0500
Dear SI gurus,
I am designing a board (approx. 6"x8.5") that has a number of buffered
signals. The critical signals have a relatively high fanout (up to about
20) that go all over the board. My goal is to eliminate
reflections/glitches in these signals which could cause double-clocking.
Is my best approach to look for a slow edge rate device (not incredibly
fast signals here, i.e. 2MHz clock lines) to allow me to treat the loads as
a lumped-load which doesn't require terminations? Or am I better off
splitting the line and terminating each signal? If I split it enough, I
can do point-to-point with series terminations on each line, but this will
use more board space. Or I can do it point-to-multipoint, grouping the
loads that are physically near each other and adding an RC termination at
the end of each group.
BTW, signal levels are 3.3V. Any particular logic family ideally suited
for this job?
Thanks in advance,
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