Re: [SI-LIST] : A Question About Power Noise.

Larry Smith (ldsmith@lisboa.eng.sun.com)
Fri, 19 Mar 1999 11:08:44 -0800 (PST)

Fabrizio - Some rather simple techniques can be used to estimate
inductance of some complex structures. I like to estimate inductances
and impedances by hand and then confirm them with EM Extractor simulations
and measurements.

First, let's emphasize that the only inductance that matters is loop
inductance. You must be able to identify a current path and _return_
current path to say anything about inductance.

A Vdd/Gnd pair of vias can be thought of as a small section of
'twin lead' transmission line. The impedance for twin lead is:

Z0 = 276 log10(D/r)

where D is the center to center spacing of the conductors and r is the
radius of one conductor. Take the crossection of a via pair where the
diameter of the via is 2r=6 mils and the center to center spacing is 50
mils. If that crossection were extended to infinity in a vacuum, it
would have an impedance of 337 Ohms by the formula above.

Next, a very handy concept to have in your back pocket is the
relationship between impedance, velocity, inductance and capacitance.
Given any two of those parameters, you can calculate the other two.
Velocity is V = 1/sqrt(LC) and impedance is Z = sqrt(L/C), L and C are
both per-unit-length. The speed of light is 3x10^8 meters/sec. Solve
the above equations for L in terms of V and C and you get:

L=Z/V.

Note that Z and V are functions of the relative dielectric constant but
L is not. The calculation gives the inductance of our via pair to be
1.12 uH/meter, or 28.5 pH per mil. Assume that the power plane pair is
an average of 10 mils below the surface of the PCB where we mount the
decoupling capacitor. The current loop then extends 10 mils into the
PCB and our via structure contributes about 285 pH of inductance.
Simulated and measured inductances for this structure are about 400 to
500 pH, so the hand calculation is optimistic, but within a factor of
2. I believe this is because we did not account for the current on the
other two sides of the loop (power planes and across the capacitor
pads).

In any case, the via structure under the decoupling capacitor
pads contributes about 0.5 nH. If we had mounted the capacitor on the
other side of a 62 mil thick board, our inductance would have been 1.77
nH. This is very close to the simulated and measured value because the
via length is a much more dominant part of the loop inductance. As already
mentioned in this thread, the capacitor height contributes between
200 and 500 pH. A similar analysis is made for Vdd/Gnd via pairs at the
ASIC site. ASIC's typically have many pairs of VDD/Gnd in parallel,
substantially reducing the inductance to the power planes.

Which brings us to the next topic: power plane spreading inductance.
It turns out that the same simple calculations can be made here also.
Capacitance between planes is well understood:

C = eR * e0 * Area / thickness

Where eR is the relative permitivity and e0 is the permitivity. For
a pair of power planes spaced 4 mils apart in a vacumm,

C = 1 * 8.854e-12/(4/39.37e3) = 87.1e-9 F/square_meter

Use the above equations but this time solve for L in terms of C and V:

L = 1/(V^2 * C) = 128 pH (per square)

Inductance of our power planes separated by 4 mils is 128 pH per
square. Interesting units.. The interpretation of this is very much
like sheet resistance that comes in Ohms per square. Draw up the
curvilinear squares for a resistive plane or inductive plane and you
can calculate the resistance between two structures or the inductance
between two structures by multiplying by the number of squares in
series and dividing by the number of squares in parallel. It turns out
that there is not too many squares between a decoupling capacitor and
an ASIC (like maybe less than one). The spreading inductance of 4 mil
power power planes is on the order of 130 pH, much less than that of
the capacitor via structure. I am not ready to go into the details,
but we have measured and simulated power plane spreading inductance and
the hand calculations are very close to the correct results.

Now let's take a look at the attachment of a decoupling capacitor to an
ASIC using surface traces. Same trick. Use a couple of 50 Ohm
lines and assume that the differential impedance is 90 Ohms.

L = Z / V = 90_ohms / 3e8_meters/sec = 300 nH/meter = 7.62 nH/inch

This is quite close to the 9.33 nH/inch that came out of my field solver.

I know this has been a long winded answer to Fabrizio's question, but I
wanted to demonstrate how some simple calculations can be used to
estimate the values we should be getting from our field solvers and
measurements. Using some very basic first principles we have
calculated that the inductances for several structures are on the
order of:

pair of surface traces 10 nH/inch
pair of vias for decap 1 nH
power plane inductance 0.1 nH

Hmmm. I know how I am going to connect my decoupling capacitors
to my ASICs..

As for the second question, some of our results are published in the
proceedings from the Electrical Perforamance of Electronic Packaging
Conference, 1998. The paper is: "ESR and ESL of Ceramic Capacitor
Applied to Decoupling Applications", Tanmoy Roy, Larry Smith.

regards,
Larry Smith
Sun Microsystems

> Date: Fri, 19 Mar 99 9:30:50 -0500
> X-Priority: 3 (Normal)
> To: <si-list@silab.eng.sun.com>
> From: "fabrizio zanella" <fzanella@fishbowl02.lss.emc.com>
> Subject: Re: [SI-LIST] : A Question About Power Noise.
> X-Incognito-SN: 1467
> X-Incognito-Version: 4.11.23
> MIME-Version: 1.0
>
> Larry, thanks for the great information about your past experiences with
> decoupling! Can you share with us how you calculate the loop inductance
> from the power planes through traces and vias to chips? This seems as it
> would be a difficult calculation.
> Also, is the material you presented at last year's Electrical Performance
> of Electronic Packaging (EPEP) conference available somewhere? It seems
> like very worthwhile reading to understand an important issue. For those of
> you who did not attend DesignCon, power noise seems to be the next big
> hurdle for signal integrity engineers to solve.
> Regards,
>
> Fabrizio Zanella
> EMC, Hardware Engineering
> fzanella@emc.com
> 508-435-2075, x4645
> -------------
> Original Text
> From: "Larry Smith" <Larry.Smith@Eng.Sun.COM>, on 3/18/99 2:17 PM:
> To: smtp@Eng@EMCHOP1[<si-list@silab.eng.sun.com>]
>
> The question is: "Is it better to connect decoupling capacitors
> directly to the power planes with vias, or to connect a chip to the
> capacitor with traces and then via to the power planes on the far side
> of the capacitor?" Doug Brooks wants answers.
>
> Been there, done that.. several years ago.. It's a little late, but I
> will report the results now.
>
> As several posters have already pointed out, the answer may be
> different for analog and digital applications, and may depend on your
> reasons for decoupling. Placement of the capacitor between the chip
> and the power planes will protect the power planes from high frequency
> noise. It is a T filter involving the capacitor and inductors (traces
> or vias) to the left and right of the capacitor. But, the filter works
> both ways. If the power planes are considered to be an ideal voltage
> source, the chip will look out through the filter and see a high
> impedance at one or more frequencies caused the parallel resonance of
> the capacitor and the far inductance. If the chip tries to draw power
> at that frequency... curtains. The failure can come in the form of a
> chip that does not work or high EMI emissions at that resonant
> frequency.
>
> I have come to the conclusion that it is much better to attach
> decoupling capacitors directly to tightly coupled (closely spaced)
> power planes. Then connect the chip in the same way. The systems I
> deal with tend to have dozens if not 100's of pairs of Vdd/Gnd
> connections from the ASIC or uP to the power planes. A very low (10's
> of pH) loop inductance from the chip to PCB power planes is established
> in this way. The planes are then decoupled with dozens of high
> frequency capacitors on low inductance pads. As discussed yesterday,
> the inductance in the capacitor/power-plane loop is under 1nH. By this
> method, we have established a sufficiently low impedance path to
> conduct charge from the capacitors to the chip, when the chip demands
> transient current. Transient demands can easily be 10 amps in 10 nSec
> = 1amp/nSec = di/dt. V=L di/dt and if we want to have much less than 1
> volt of noise on our power supply, the inductance had better be much
> less than 1 nH.
>
> Let's look at the numbers for the alternative approach. A pair of 12
> mil wide surface traces that are spaced 6 mils apart have a loop
> inductance that is 9.33 nH/inch (by my extractor). So, if the pair of
> traces are more than 50 mils long, we have exceeded the partial
> inductance due to the capacitor pads and vias used to hook a capacitor
> to power planes. It will be very difficult to place capacitors within
> 50 mils of the power pins on an ASIC.
>
> But I tried to do it one time... I had about a dozen Vdd/Gnd pairs on
> the inside rows of a CBGA. I used vias near the Vdd/Gnd solder bumps
> to get to the back side of the PCB. I used very wide traces to pass
> underneath two sets of decoupling capacitor pads, thinking that I was
> going to make a very nice filter. Finite element analysis (after the
> artwork was released, of course) showed that the loop inductance from
> the power planes through the traces and vias to the chip solderballs
> was over 9 nH..! The system actually worked, but I breathed a sigh of
> relief when the project was canceled. The power planes were nice and
> clean noise wise, but there were certain frequencies where the chip was
> not allowed to draw current, and customer code is kind of hard to
> predict. Spice simulation of the structure showed some pretty ugly
> power waveforms at the chip. ...Well, I'll never do that again.
>
> Doug - we appreciate fine work your company has done and the published
> material in Printed Circuit Design magazine. I believe the whole
> industry benefits from open discussion like this. We have published
> a portion of our work at last year's EPEP conference in the form
> of a paper and class on power distribution. If things go well, we
> will have a full length paper in the CPMT journal next August that
> deals more with the decoupling and power distribution topic.
>
> regards,
> Larry Smith
> Sun Microsystems
>
>
>
> > X-Sender: doug@mail.eskimo.com
> > Date: Wed, 17 Mar 1999 16:53:41 -0800
> > To: Raymond.Anderson@eng.sun.com, si-list@silab.eng.sun.com
> > From: Doug Brooks <doug@eskimo.com>
> > Subject: Re: [SI-LIST] : A Question About Power Noise.
> > Mime-Version: 1.0
> >
> > Perhaps you can hear my chuckling in the background, here.
> >
> > Once apon a time, I advocated running traces from caps to devices. My
> > reason, primarily, was to keep noise off the planes. I took quite a bit
> of
> > heat from many people who said that routing to the plane was a MUCH lower
> > inductance way to route.
> >
> > Now you provide information that (might) suggest that even if the plane
> had
> > NO inductance, there is inductance in the vias getting back and forth
> from
> > the planes to the caps and devices. So the planes, in the total picture
> > might not be the lowest inductance way to route afterall. And,
> > interestingly enough, Michael Zhang then says the HP (Printer Division)
> > routes using traces to keep noise off the plane (If I understood his
> e-mail
> > properly).
> >
> > Then the argument shifts from inductance to loop area (a view that, at
> > least I, hadn't heard before). This, in fact, might be a pretty good
> > argument. Even if the loops on the planes are of similar length, there is
> > at least some shielding there that does not exist around surface traces.
> >
> > So here is my challenge to some of you. My company has tried to design,
> > test, and report on two areas in the past --- the effects of vias on
> PCB's,
> > and the effects of 90 degree corners on PCB's. The results of both
> > investigations appeared in PCB Design and copies are available on our web
> > site. My company does not have the resources to conduct an experiment on
> > bypass caps (although we will certainly participate to the extent we can
> > help). Some of you DO have the resources. So lets have a few people
> > associated with this group figure out how to design and control an
> > experiment that will resolve these issues once and for all, and share
> those
> > results with the rest of the community.
> >
> > I hope someone picks up the challenge.
> >
> > Doug Brooks
> > .
> > ****************************************************
> > Doug Brooks, President doug@eskimo.com
> > UltraCAD Design, Inc. http://www.ultracad.com
> >
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