I agree that 20 mV can be an EMI disaster. To fully evaluate this
problem, we would have to know the size of the power planes and the
losses. The disturbance between the power planes created by signal
via return current diminishes greatly as it propagates out radially.
If the via continues to create disturbances at a repetitive frequency,
it can set up resonances on the power planes. Bare power planes act
like a pretty high Q structure. But when populated with ASICs and lots
of decoupling capacitors, there is a fair amount of loss. So the
20 mV of local noise between power planes does not create as much EMI
as you might think. If it did, our EMI problem would be a lot worse
than what we observe with measurement.
You have reported that a single trace produced a 26 dB difference in
the emissions for a test board. Was the trace properly terminated?
Did it have a good reference plane and path for return current for the
whole length of the trace? I have always thought that a well
terminated trace (either microstrip or stripline) with a good return
current path should not produce much EMI.
regards,
Larry
> From: "Douglas C. Smith" <doug@dsmith.org>
>
> You mention that 20 mV drop is not bad. That is about 10 times the
> amount that can cause an emc problem if concentrated at one frequency.
> That may be close to the case at the resonant frequency of the 2 plane
> structure. In my earlier reply, it was noted that a single trace
> produced a 26 dB difference in emissions for a test board.
>
> Doug
>
> Larry Smith wrote:
> >
> > Eric - The situation you have described is completely true. Return
> > current associated with a trace via must jump from one reference plane
> > to another in stackup 2 and 3 below and in most of the stackups in use
> > in the computer industry today. This is not to much of a problem for a
> > single trace, but can be a major problem for a wide bus (perhaps 64
> > signals) with similar vias and all of the signals switching the same
> > way at the same time. It becomes an SSN noise problem that I call the
> > "power plane bounce" issue. This happens not only at a via but also at
> > a connector and at electronic packages containing drivers or
> > receivers.
> >
> > You are also correct in saying that the return current must come
> > through a capacitance somewhere. The parallel plate capacitance
> > between the planes is generally sufficient for one signal for a short
> > time period (several nSec). But if there is a far end parallel
> > termination, DC current may have to go through this capacitance for a
> > long period of time. Discrete capacitors may be required.
> >
> > How close does a capacitor have to be to be effective? First, look at
> > the time of flight of energy on the power planes: 6 inches/nSec in FR4
> > dielectric. The return current associated with the via creates a
> > radial disturbance that emanates out from the via at that velocity. It
> > will take at least 2 time of flights for the capacitor to be
> > effective: one time of flight for the disturbance to reach the
> > capacitor and another for charge to make it back to the via. For a
> > capacitor to be effective during a 1 nSec rise time, it must be within
> > 3 inches of the via.
> >
> > The loop inductance from a capacitor to the power planes is probably
> > more important than the capacitance. Suppose we have a 50 Ohm trace
> > and 1V/nSec edge. The current and return current for the trace is
> > 1V/50Ohms = 20 mA. Most of that return current has to jump planes in
> > stackup 2 and all of the current must jump planes in stackup 3. The
> > inductance of a discrete capacitor is determined mostly by the pads and
> > vias to the power planes. If the power planes are reasonably near the
> > surface of the PCB and the distance between vias is short, the
> > inductance in the capacitor/power-plane loop is around 1 nH. The
> > voltage drop across the loop inductance is V=L*di/dt = 1nH*.02A/1nSec =
> > 20mV, not bad. But if 10 vias are involved then we have 10X the
> > current and 200mV of drop across the capacitor loop inductance.
> >
> > I have come to the conclusion that the power plane capacitance must
> > conduct the return current during the rise time and for the first
> > several nSec. After that, the time constant involving the loop
> > inductance of the capacitor will allow it to be effective. The amount
> > of capacitance required can be calculated by I=C*dv/dt.
> >
> > The interplane capacitance is easily calculated from
> > C=e0*eR*Area/thickness. Calculate the capacitance and then calculate
> > the voltage drop from dv=I*dt/C. In this case, dt is the amount of
> > time that the interplane capacitance must support the return current.
> > For source terminated lines (open circuit far end) it will just be a
> > few nSec. For far end terminated lines, the return current goes on for
> > ever and discrete capacitors will be required. Eventually, the return
> > path involves the power supply, but it takes micro seconds before
> > it can respond.
> >
> > An interesting side note, the power plane capacitance is not all
> > available immediately. As described above, only the capacitance within
> > a 3 inch radius is available in 1 nSec. If we wait long enough, the
> > radial disturbance on the power plane reaches the edges of the board
> > and bounces back. Power plane resonance's occur. Some other responses
> > to the list have already mentioned that the planes can appear to be
> > inductive at certain frequencies and at certain positions on the
> > board. The best way to look at the planes is by impedance rather than
> > capacitance calculations. But that is a long discussion and this note
> > has gotten too long already..
> >
> > regards,
> > Larry Smith
> > Sun Microsystems
> >
> > PS - Mike Jenkins has already mentioned that many of these issues
> > go away with differential signals (true!). But for those 'gluttons for
> > punishment' who are trying to push single ended signals as far as
> > they can, this stuff is real important.
> >
> > > Hi,
> > >
> > > Consider a few different partial stackups each with a via:
> > >
> > >
> > > Stackup 1
> > > | |----------- trace B
> > > plane =========== | | ==========
> > > trace A ------------| |
> > >
> > >
> > > Stackup 2
> > >
> > > plane =========== | | ==========
> > > trace A ------------| |
> > > trace B | |-----------
> > > plane =========== | | ==========
> > >
> > >
> > > Stackup 3
> > > | |----------- trace B
> > > plane =========== | | ==========
> > > plane =========== | | ==========
> > > trace A ------------| |
> > >
> > >
> > > In stackup 1, the return currents for trace A and trace B just need to
> > > migrate to the other side of the the plane which is fairly easy and has a
> > > low impedance. However, this stackup is not preferred for PCB
> > > manufacturability reasons.
> > >
> > > In stackups 2 and 3, the return current for trace A moving to trace B has
> > > to jump planes. The only place that can occur is via a capacitance. Some
> > > capacitance is provided by the interplane capacitance which works better
in
> > > stackup 3 than it does in stackup 2. Otherwise, a nearby bypass cap must
> > > be found. The farther away the cap is, the larger the inductance (and
> > > impedance) of the return current path.
> > >
> > > My system is running pretty fast (> 1 Gbps).
> > >
> > > My questions:
> > >
> > > 1. Is what I've described generally true?
> > >
> > > 2. How could one analyze how far away a "nearby" cap can be and not
degrade
> > > the signal too much?
> > >
> > > 3. How does the value of the cap affect this? Clearly we want a low
> > > inductance package. Do I just go for the largest capacitance that fits in
> > > a low-inductance package?
> > >
> > > 4. How could one analyze if the interplane capacitance is sufficient for
> > > this purpose?
> > >
> > > -Eric
> > >
> > > --
> > >
> > > Eric Goodill Cisco Systems M/S SJ-N2
> > > mailto:ericg@cisco.com 170 W Tasman Dr
> > > voice: (408) 527-3460 San Jose CA 95134-1706
> > > fax: (408) 527-3460 (yes, the same)
> >
> > **** To unsubscribe from si-list: send e-mail to
majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list,
for more help, put HELP. si-list archives are accessible at
http://www.qsl.net/wb6tpu/si-list ****
>
> --
> -----------------------------------------------------------
> ___ _ Doug Smith
> \ / ) P.O. Box 1457
> ========= Los Gatos, CA 95031-1457
> _ / \ / \ _ TEL/FAX: 408-356-4186/358-3799
> / /\ \ ] / /\ \ Mobile: 408-858-4528
> | q-----( ) | o | Email: doug@dsmith.org
> \ _ / ] \ _ / Website: http://www.dsmith.org
> -----------------------------------------------------------
>
> **** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com.
In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP.
si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****
>
**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****