Re: [SI-LIST] : A Question About Power Noise.

Fred Balistreri (fred@apsimtech.com)
Wed, 17 Mar 1999 17:25:44 -0800

Doug Brooks wrote:
>
> Perhaps you can hear my chuckling in the background, here.
>
> Once apon a time, I advocated running traces from caps to devices. My
> reason, primarily, was to keep noise off the planes. I took quite a bit of
> heat from many people who said that routing to the plane was a MUCH lower
> inductance way to route.
>
> Now you provide information that (might) suggest that even if the plane had
> NO inductance, there is inductance in the vias getting back and forth from
> the planes to the caps and devices. So the planes, in the total picture
> might not be the lowest inductance way to route afterall. And,
> interestingly enough, Michael Zhang then says the HP (Printer Division)
> routes using traces to keep noise off the plane (If I understood his e-mail
> properly).
>
> Then the argument shifts from inductance to loop area (a view that, at
> least I, hadn't heard before). This, in fact, might be a pretty good
> argument. Even if the loops on the planes are of similar length, there is
> at least some shielding there that does not exist around surface traces.
>
> So here is my challenge to some of you. My company has tried to design,
> test, and report on two areas in the past --- the effects of vias on PCB's,
> and the effects of 90 degree corners on PCB's. The results of both
> investigations appeared in PCB Design and copies are available on our web
> site. My company does not have the resources to conduct an experiment on
> bypass caps (although we will certainly participate to the extent we can
> help). Some of you DO have the resources. So lets have a few people
> associated with this group figure out how to design and control an
> experiment that will resolve these issues once and for all, and share those
> results with the rest of the community.
>
> I hope someone picks up the challenge.
>
> Doug Brooks
> .
> ****************************************************
> Doug Brooks, President doug@eskimo.com
> UltraCAD Design, Inc. http://www.ultracad.com
>
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There is no known solution for all given problems. The application will
dictate the final solution. It is clear that from some Analog design
points of view the solution may be quite different than CMOS switching
digital devices. This should not be a surprise. They are very different
animals. As for the challenge, given the above only a particuliar
given problem can be solved. So there is not going to be total solution
for everyone. Indeed there was an application listed here where Dr.
Johnson's suggestions regarding this issue were followed. The circuit
did not work. The final solution was to break a fundamental rule in
the book. That application had mixed analog and digital elements. So
who do you fault? Dr. Johnson's book says DIGITAL design.

Best Regards,

-- 
Fred Balistreri
fred@apsimtech.com

http://www.apsimtech.com

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