RE: [SI-LIST] : high-power board

tomda (tom_dagostino@mentorg.com)
Tue, 6 Apr 1999 07:33:44 -0700

A good model of this kind of board is the Cray 1 Super Computer. They used
multi layer boards bonded to a copper core that had cooling fluid running
through it. Theirs was an ECL design so the power problems were not so bad
but the heat removal issues were solved albeit rather expensively.

Tom Dagostino

-----Original Message-----
From: D. C. Sessions [SMTP:dc.sessions@vlsi.com]
Sent: Monday, April 05, 1999 9:22 AM
To: si-list@silab.eng.sun.com
Subject: Re: [SI-LIST] : high-power board

Pat Zabinski wrote:
>
> We're looking into a board that has much higher power requirements
> than we're familiar with, and I'm looking for some advice. Here's
> a summary of the board:
>
> * roughly 1000 Watts (1 KW) off a single +5 V DC supply
> * full-swing CMOS
> * ~50 ASICs
> * 200 MHz clock and data paths
> * up to 300 simultaneous switching outputs per chip
> * between 12x12 and 24x24 inch multi-layer PCB
> * ASIC packages have yet to be determined/designed
>
> To some extent, we have a good handle on the standard SI issues, but
> we're looking for input in two areas: decoupling and power.
>
> With 300 full-swing switching outputs per chip, what's the best
> (or a good) way to decouple the supply? First, at the chip-level.
> Second, at the board-level.

Chip-level decoupling won't help with your SSO, although it will
keep the onchip (core) supply in better shape. I most
profoundly hope you're using reasonable packages such as the
copper-slug cavity-down ball grid parts (what we call HBGA).
You REALLY need the low theta(jc) and low pin inductance.

My first suggestion is to ditch the 5v supply. You're paying a
premium for obsolete parts and then having to pour in more than
twice the power compared to 3.3v parts -- and in your case that
power density is a show-stopper. Of course, you probably can't
change it by now. Bummer.

> At this high of power level, what are the primary concerns?

Desoldering the ICs. Delaminating the PWB.

> How
> do we best address them? Is there a limit on how much current
> a half-ounce copper sheet in FR4 can tolerate?

Yup, and you're probably way past it. Pay particular attention
to the power path through your via field around the ICs; we've
seen some parts suck enough juice to blister the FR4 on much
lower-power applications than yours. If at all possible go
to multiple power planes with 2 oz copper. Not only will you
get better power distribution but it'll spread the heat somewhat
as well.

> How much current
> can I push through a standard via before it melts?

More than you can afford in terms of IR and Ldi/dt drop.
The vias aren't the worst of the bottleneck; it's the gaps
between them that are likely to kill ya.

> How can
> we effectively remove the heat?

Water jackets. Freon immersion.

Look, I'm not joking. 1000w is the kind of power that you use
for heating a small room. With a high-velocity fan behind it
my little ceramic heater still glows cherry red with 750 watts;
you are going to need a large external chiller to keep under
150C junction temps with anything aircooled.

--
D. C. Sessions
dc.sessions@vlsi.com

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****

**** To unsubscribe from si-list: send e-mail to majordomo@silab.eng.sun.com. In the BODY of message put: UNSUBSCRIBE si-list, for more help, put HELP. si-list archives are accessible at http://www.qsl.net/wb6tpu/si-list ****