Recently, I reviewed an interesting paper by Dr. Howard Johnson, which
had been presented at DesignCon99. It is a PDF file (busarch.pdf)
entitled: "Bus Architecture & Timing", available at the High Speed
Design Web Site: http://www.signcon.com/
The paper evaluates design difficulty of several different buses in
terms of bus timing ratio defined by [( bus delay ) / (clock period)].
The results are summarized below:
Bus: PC-AT, Bus timing ratio: 0.008,
Mode: Slow , Design: Easy;
Bus: PCI, Bus timing ratio: 0.062,
Mode: Skew, Design: -------;
Bus: RAMbus, Bus timing ratio: 2.5,
Mode: Distributed clock, Design: -------;
Bus: Ethernet 10BASE-5, Bus timing ratio: 100, Mode:
Time-space, Design: More difficult;
In the final slide it is stated: " The ratio (bus delay)/(clock
period) is a key indicator of bus design difficulty".
Admittedly, I was surprised by the conclusion and method of analysis
employed by this article. Here, a parameter dependent on the PERIOD is
used to evaluate difficulty of bus design. It seems to me that
"Critical Length" is preferable for appraisal of design (or simulation)
complexity of a high speed bus architecture. The Critical Length Lc
varies with the RISE TIME (i.e. Lc = k * Tr / D , where Tr is the Rise
Time ), rather than with the period or frequency.
Your comments are appreciated.
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