Re: [SI-LIST] : coming up with average power estimates for buffers

[email protected]
Tue, 3 Aug 1999 13:29:12 -0500

Since every positive transition can be paired up with a negative transition
(possibly of a different buffer on the same bus), I'd stick with the simple

Now lets suppose you characterize a large number of buffers and compute
both the mean and the standard deviation of the power. Lets suppose there
were two classes, one with a mean power of 1mW and a SD (standard
of 20uW. The other class was 0.5 mW with a SD of 15uW.

Lets assume each ASIC has 1000 buffers. Assuming that the buffers in a
specific ASIC all have the same deviation you would calculate that the
type will dissipate 1W with a SD of 0.2W and the other will dissipate 0.5W
a SD of 0.15W.

Lets say you had 50 of the former and 75 of the latter.

Your mean power would be 50*1W + 75*.5mW = 87.5 W
Here is where you would use the sum of the squares:
The overall SD would be sqrt [50*(.20^2) + 75*(.15^2)] = 1.92 W

Now lets say you wanted 6 sigma assurance that you have a
big enough power supply you might compute 87.5 + 6*1.92 = 99W round to

With the apparently large number of ASIC's in your system, the ratio
of the SD to the mean power will probably be so small that you
ignore the SD's unless of course all your ASIC's come from the
same batch in which case all your deviations might be in the
same direction.

- - - - - Original Message Date 08/02/99 10:57:01 AM - - - - -

I'm working on a rather large system (over 50,000 Watts!), and we
are trying to come up with some detailed power estimates for
each component.

The system is essentially comprised of LOTS(!) of identical
parallel processing ASICs, each ASIC having roughly 600 I/O.
The basic I/O is full-swing CMOS with a 2.5 VDD supply running
at roughly 100 Mbps. A small change in one ASIC will have
a three-orders of magnitude higher impact on the system, so we need
to pay very close attention to details. The I/O have been
designed and tweaked to account for impedance, edge rates,
packaging effects, etc., so we have a high level of confidence
they are going to work; at this point, we simply need to
obtain a power estimate for them.

In order to come up with good system-level power estimates (which
will determine cooling requirements and power supply requirements),
we need to have an accurate ASIC power estimate. We've got pretty
good numbers for the core circuitry, but we're trying to develop
an estimate for the custom I/O buffers.

To get the power for one buffer, we simulate the buffer with
a 1010101... pattern, toggling every possible bit period.
The buffer is loaded with an average-length transmission
line, and we use spice to plot the power vs time for at
least two bit-transitions. Overall, we get a power
vs time plot that is relatively flat except during the logic
transitions (no surprise here), and the peaks vary in amplitude
depending upon a rising or falling edge.

In the past, we have used the "simple average" power, meaning
taking the integral of the power over two bit periods (to ensure
we've captured one falling and one rising edge)and dividing
it by the time. We have used this figure as
our average power for the worst-case-bit-pattern.

However, a colleague recently suggested using the "RMS average"
of the power, which is computed slightly differently. For our
case, the RMS average resulted in a power estimate that was
50% higher than the average value.

>From my experience, taking the integral of the power curve will
result in the effective energy consumed by the buffer, and dividing
this by the time will provide the average power. However,
RMS is used so frequently in power estimates, I could not provide
a good answer why it shouldn't be used.

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