Re: [SI-LIST] : An Interesting Presentation

Michael Nagel (mina@force.de)
Tue, 20 Apr 1999 16:00:26 +0200

I mean rise- and falltime when I talk about "fast" and "slow".

Just my 2 cents ...

Michael

> From lmichael@techmail.gdc.com Tue Apr 20 15:41:04 1999
> Date: Tue, 20 Apr 1999 09:28:42 -0400
> From: Laurence Michaels <lmichael@techmail.gdc.com>
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> Subject: Re: [SI-LIST] : An Interesting Presentation
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> One of the things a slower bus timing (with less stringent timing
> requirements at RAM chip inputs for instance), is that it allows for
> more ringing, and other things that are bad from an SI viewpoint.
> There's more time for the data signals to settle down to a reasonable
> state before the data gets clocked in.
>
> So, in buses with loose timing requirements, SI is almost ignorable on
> data lines, as long as the clocks are good, and the data has enough time
> to settle.
>
> Clock tree design is left as an exercise for the reader.
>
> Comments?
>
> -- Laurence
>
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