Re: [SI-LIST] : A Question About Power Noise.

David Chengson (chengson@juniper.net)
Wed, 17 Mar 1999 16:50:10 -0800 (PST)

Gents-
Was wondering if anyone has compared IDC capacitors versus 0612
capacitors of the same values when placed next to ASICs.

The IDCs need 8 vias, which swiss-cheese the power/ground
plane near the ASICs, and create routing blockages. For 1mm
pitch ASICs, even small anti-pads (30 mils) contribute to

The 0612 caps effectiveness are limited by the number of vias
connecting to power/ground planes.

And more philosophically...
I believe on-chip caps, followed by on-package caps, followed by
PWB distributed capacitance are the most effective capacitor
types for reducing on-chip ASIC (core) noise, which is probably
the largest noise sources in reasonably well designed systems.

Discrete board caps are probably the least effective capacitor
type to reduce on-chip noise.

My $.02

Dave Chengson
Juniper Networks.
chengson@juniper.net
> From owner-si-list@silab.eng.sun.com Wed Mar 17 15:48 PST 1999
> Date: Wed, 17 Mar 1999 15:09:34 -0800 (PST)
> From: Ray Anderson <Raymond.Anderson@Eng.Sun.COM>
> Subject: Re: [SI-LIST] : A Question About Power Noise.
> To: si-list@silab.eng.sun.com
> Cc: doug@eskimo.com
> MIME-Version: 1.0
> Content-MD5: ezjiWewoPUgyBWQuyKVNow==
>
>
> >
> > OK Ray. Here is a loaded question for you. (See below)
> >
> ... snip snip ...
> >
> >
> > There has been considerable discussion about how to mount/route a bypass
> > cap. One theory is to run traces from the cap to the device and then vias
> > from the cap to the plane. The other theory is to run vias to the plane
> > from both the device and the bypass cap and let the currents flow over the
> > 'low inductance' plane.
> >
> > Now, if the highest inductance part of the path is the pad/via, would that
> > favor running (wide) traces from the cap directly to the device, since that
> > eliminates two vias between the cap and the device? A wide, short path only
> > has a few nH inductance (I think).
> >
> > Doug Brooks
>
>
> Just spoke with my colleague Larry smith about your question
> and the concensus is that it is a BAD idea to run traces from
> the capacitor to the chip and then connect the composite
> mess to the planes via vias .
>
>
> Why?? Loop area. The loop area of the current path that
> describes the circuit from plane 1 up through a via, through
> a trace, through a capacitor, back through another trace and
> thence to the other plane is much larger than the loop area
> from a plane, through a via, through a cap and then to the
> other plane.
>
> Why do we care about loop area? Because the bigger the loop,
> the more lines of magnetic flux and hence the higher the inductance.
> This translates to a lower SRF among other things. These other
> things include making the Q of the bypass higher and hence of
> lower bandwidth. This requires the use of more capacitors to
> achieve the same bypass effectiveness since our goal is
> to create a broadband low impedance for the power distribution
> system.
>
> To supplement all the buzzwords, Larry had empirical experience
> in that he tried it wrong way once upon a time and swears
> he will never do it again..
>
> Run your chip power pins directly to the planes. Run your
> decoupling caps directly to the planes (while minimizing the
> current loop area and via length).
>
> -Ray Anderson
>
>
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