You're all familiar with this picture of high-frequency return current bunching
up under the signal trace, right? According to the picture, it dies off pretty
quickly as you move along the x-axis away from the trace. Well, I've been
considering rules for the area density of ground vias and decoupling capacitors,
and it occurs to me that if this picture were true, then the only place for a
ground via or capacitor is within 2-3 trace widths of the signal via in
question. (Which is, for most of our applications, absurd.) Otherwise I'd be
forcing the return current out of that very tight loop, increasing the
inductance, adding a discontinuity, generating plane noise, emissions, and all
those nasty things. Now, I know that boards work quite well up to a few hundred
MHz with considerably less than 100 de-caps per square inch! So where's the
discrepancy? Is there a hole in my fairly simplistic, qualitative analysis? Or
is this just like everything else: knowing how some parameter varies between
the end cases is much harder than analyzing the end cases?
On another tangent, I believe 2-D field solvers make the assumption that the
return current is evenly distributed across the surface of a plane when you ask
them to compute C, L and Z for a given cross-section. Doesn't this also
conflict with the high-frequency current distribution picture?
Eagerly awaiting your answers and hoping I have time to read them,
Greg Edlund
Advisory Engineer, Critical Net Analysis
IBM
3650 Hwy. 52 N, Dept. HDC
Rochester, MN 55901
gedlund@us.ibm.com
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