RE: [SI-LIST] : Terminating a bidirectional bus

Fox, Michael J (michael.j.fox@intel.com)
Mon, 3 May 1999 12:32:34 -0700

Arrigo,
I'd recommend looking at FPGA and SRAM's DC requirements carefully. A
series termination will cause a level shift. Unless you are using
reflective-mode transmission or the buffers are internally terminated, I'd
recommend parallel terminating both ends of the bus.
But that's only good if both chips have the same DC requirements. If they
have different DC requirements tell me about it and I'll give you that
lecture.

Michael

-----Original Message-----
From: Arrigo Benedetti [mailto:arrigo@vision.caltech.edu]
Sent: Monday, May 03, 1999 9:21 AM
To: si-list@silab.eng.sun.com
Subject: [SI-LIST] : Terminating a bidirectional bus

Dear all,

I would like to know you opinion on this issue. I am interfacing a
state of the art FPGA with a high speed synchronous SRAM device. Since
the interface is bidirectional (the FPGA will read and write data to
the memory) I was wondering what is is the best way to terminate this
bus. My intuition is that if the data lines are not very long, then a
series termination near the FPGA end could have an effect similar to a
series termination near the memory end when the memory is driving the
bus.

I've in the the standard SI book, and haven't found any hint on the
problem.

thanks in advance

-Arrigo Benedetti

--
Dr. Arrigo Benedetti                e-mail: arrigo@vision.caltech.edu
Caltech, MS 136-93	  			phone: (626) 395-3695
Pasadena, CA 91125	  			fax:   (626) 795-8649

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