RE: [SI-LIST] : Decoupling strategy in tight spaces

Greim, Michael ([email protected])
Fri, 17 Sep 1999 09:08:53 -0400

No need to apologize, I realized what you were talking about yesterday.
For the interested readers in our audience. This is the refered to article.

Your drawing for the most part is correct. I like to advocate placing
the vias in the pads of the cap to again minimize inductance and given
the large nature of the pad and the small nature of the via (10-13 mils)
you're not going to wick any solder off while increasing the frequency
response of the decoupling. The same can be said for SMT connectors
where the pad is big enough to accomodate a via.

All things being assumed and equal, we are both right to a certain

We both agree that inductance is the enemy at high frequency and
there is a number of ways to solve that problem, and at some point
in time you reach a point of diminishing returns in what you get for
your effort. The simple battle comes down to which method adds
additional inductance to the path. It is simply a question of number
and type of via vs capacitor proximity and trace topology between the
device pin and the capacitor.

Now, let me throw you a curve. Fanning out a SMT part (and for the
sake of argument lets talk QFPs since unless power pins are on the
outer row of balls, my scheme won't work for BGAs), you are already
commited to fanout etch and via to the plane. That being said, and
since we are in violent agreement that current will follow the path of
least inductance, why not use the capacitor pad to sink multiple vias
and now you basically have both things together (which is pretty much
what I was advocating albeit not clearly). You are already commited
to the fanout etch on the device, now you have more vias to get to
that power plane (less inductance) and with my department of redun-
dancy department hat on, you have eliminated a large number of
useless vias, which now increases the route-ability of the board,
shortening traces and improving SI. Whaddya think?

Of course, there is an optimal situation when the capacitor magically
spans the power pins on a device such that this topology can be
used to attach to power and ground pins.

Best Regards,

Michael C. Greim Consulting Engineer
Mercury Computer Systems, Inc email: [email protected]
199 Riverneck Road V:
Chelmsford, MA 01824-2820 F: 978-256-4778

> -----Original Message-----
> From: sweir [SMTP:[email protected]]
> Sent: Thursday, September 16, 1999 8:07 PM
> To: Greim, Michael
> Subject: RE: [SI-LIST] : Decoupling strategy in tight spaces
> Michael,
> I apologize that what I was referring to actually turned-out to be one of
> Dr. Johnson's newsletters, and not his book.
> I believe that we agree that we want to minimize the impedance between our
> load and its energy source across any frequency range of significance. I
> believe that our disagreement is on what implementation specifics will get
> us there. I want to confirm that we are looking at the same picture:
> I believe this is a picture of what you advocate with the reverse geometry
> caps:
> -----
> o| |o
> --- | |o
> |pad|--| cap |o
> --- | |o
> o| |o
> -----
> Where o represent vias.
> Given:
> 1. The interconnect inductance is the ultimate limiting factor.
> 2. The capacitor's internal inductance is much greater than the almost
> zero inductance of solid planes.
> 3. Almost universally, the ground return current supplied by the capacitor
> to the part will have to traverse a portion of the ground plane to a via
> nearest the ground pad.
> I argue that the wide-band impedance seen by the device pad is impaired
> unless the pad vias to the power plane with as short a connection as
> possible:
> -----
> o| |o
> --- o| |o
> |pad|-o o| cap |o
> --- o| |o
> o| |o
> -----
> The planes provide a much lower impedance at high frequencies than any
> single capacitor, and as you note we can get a respectable amount of
> buried capacitance pretty easily. So, to carry power to our load at the
> lowest impedance we want to absolutely minimize the inductance inserted
> between the pad and the planes.
> That means placing the via as close as possible to the pad. The planes
> supply the load. The capacitors recharge the planes. Placing the
> capacitors close to the load reduces the droop caused by the finite local
> capacitance of the planes.
> I interpret 8.2.4 as pointing out that a planar connection has low
> inductance. Those capacitors were devised for PLCC and through hole parts
> which have 5-10X the lead inductance of BGA's.
> I do not have a copy of the newsletter issue to which I referred but may
> have saved it at home. If you would like, I can look for it this weekend.
> Regards,
> Steve.

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