RE: [SI-LIST] : A Question About Power Noise.

Chan, Michael (Michael.Chan@COMPAQ.com)
Fri, 5 Mar 1999 09:42:07 -0600

Dear Nirmal:
Maybe Kidong's meaning of power noise is for the purpose
of reducing EMC/EMI type of noise, not SSN noise. However, an inductor or
ferrite bead on the power/ground pins can create a potential problem for the
chip if the chip has PLLs inside.

Regards,
Michael Chan

> -----Original Message-----
> From: Nirmal Jain [SMTP:nirmal@ansoft.com]
> Sent: Friday, March 05, 1999 8:35 AM
> To: kidong lee
> Cc: si-list@silab.eng.sun.com
> Subject: Re: [SI-LIST] : A Question About Power Noise.
>
> Dear Kidong,
>
> I have not heard of adding inductors in series with GND or VCC to reduce
> the ground bounce or SSN. In fact
> this would increase your power/ground noise.
>
> The voltage drop in the VSS and GND planes is given by Leff * di/dt where
> L is the effective inductance for a particular switching pattern. If you
> add L in series, your effective L is going to increase and so is the
> noise.
>
> Different techniques used to reduce this noise are :-
>
> Driver Design : Reduce the speed and drive strength of the driver, make
> your receivers more immune to noise!
> Architecture : Reduce the number of simulataneously switching drivers
> Package/MCM/Chip Design :Use decoupling capacitors close to the switching
> drivers
> Layout Design: Minimize holes/openings in the GND/VCC planes
> Minimize the length of currens paths on the
> GND/VCC planes or traces
> Chip Design : Use substrate taps
>
> Refer to "SSN of CMOS devices and Systems" by Ramesh and John Prince. Hope
> it helps
>
> Regards
>
> Nirmal Jain
> Ansoft Corp
> (412) 261-3200 X129
>
>
> kidong lee wrote:
>
> > Hello everybody!
> >
> > In order to reduce power noise, one uses usually a capacitor between VCC
> > and GND or(and) adds an inductor to VCC in series.
> > Then, how about adding an inductor to GND, too ?
> > Does It work well or not ?
> > Does Anybody have an answer ?
> > Please reply to me.
> >
> > Thank you!
> >
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