For those who are interested in what IC designers are doing to reduce SI problems there is a paper from HP about HSTL(High Speed Transceiver Logic) device with on chip controlled impedance.
Paper reference: HP journal August 98, Theory and design of CMOS HSTL I/O Pads.
Maybe available on there web www.hp.com/hpj/journal.html.
-- Philippe Poulet Hardware Engineer RICOH Corp 2071 Concourse Dr San Jose CA95131-1817 Ph: (408) 944-3347 Fax: (408) 434-5390
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