Re: [SI-LIST] : How to simulate the jitter of the part?

HaroldLSJ@aol.com
Thu, 24 Jun 1999 00:02:04 EDT

Shubin,

Just some random thoughts. First, the 100ELT22 translates from TTL to PECL.
TTL or CMOS input signals will have very high levels of jitter and do not
expect the 100ELT to make it better. Jitter levels of ECL or PECL circuits
that I have measured are generally in the 1 picosec to 10 picosec peak-peak
(cycle to cycle) range because bipolar ECL has higher gain than a CMOS design
and because it is non-saturated logic. Any TTL or CMOS saturated logic
source will be one to two orders of magnitude worse in jitter. Good low
noise crystal oscillators have about 50 peak-peak picosec of jitter but can
be as high as 150 picosec peak-peak. Once you have converted to ECL or PECL
your noise should not get worse than it was at the input to the 100ELT22
unless you have noise on your power lines. Remember that ECL or PECL is high
speed analog nonsaturated logic.

Model your noise either by generating a large file of digital input signal
with Gaussian variation in the transition times (best method) or add a
Gaussian generator which models you input jitter to the threshold level of
the model. Run your simulation and generate a large file of time data. Next
import the simulation data into matlab or other similar program and generate
statistical analysis of the output cycle to cycle jitter in the data.
Complete analysis would also include thermal noise generators, noise on the
power lines and load impedance mismatch in your simulation.

Harold Snyder
Physicist & Consultant
Physical Solutions

Begin Included Message:
==========================
> Subj: [SI-LIST] : How to simulate the jitter of the part?
> Date: 6/23/99 9:27:13 PM Central Daylight Time
> From: liushb@263.net (Shubin Liu)
> Sender: owner-si-list@silab.eng.sun.com
> Reply-to: si-list@silab.eng.sun.com
> To: Si-list@silab.eng.sun.com (A Signal Integrity Email list)
>
> Dear lists,
> Because I need to predict the jitter of MC100ELT22 before I decide to
> apply it as a translator of clock signal . I haved downloaded the SPICE
model
> of the part ( which is in Motorola's application note : AN1596 ) , but I do
> not know how to add a stochastic jitter to a clock signal and how to
simulate
> the jitter of the part with the MicroSim PSPICE . So I wonder if anyone can
> give me some advice on whether I can make a simulation of jitter using the
> part's SPICE model , and , if it can work , how to do it ?
>
> Thanks in advance for any help
>
> ------------------------------------------------------------------
> ----------------------------- Shubin Liu
> _/_/_/_/ _/_/_/_/ _/ Fast Electronics Laboratory
> _/ _/ _/ Dept. of Modern Physics of USTC
> _/_/_/ _/_/_/ _/ P.O.Box 4
> _/ _/ _/ Road Huangshan
> _/ _/_/_/_/ _/_/_/_/ University of Science&Technology
> of China
> Fast Electronics Laboratory Heifei, Anhui, P.R.China, 230027
> ----------------------------- Tel: 0551-3601273----3031
> -------------------------------- E-Mail: liushb@263.net
> LAB Phone: 0551-3603114 liushb@21cn.com
> URL: http://www.felab.ustc.edu.cn liushb@netease.com
> ------------------------------------------------------------------
==========================
End Included Message.

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