Re: [SI-LIST] : Stackup Extraction

Patrick Riffault (riffault@cadence.com)
Mon, 16 Aug 1999 07:46:54 -0400

At 08:10 AM 8/15/99 -0700, Abe Riazi wrote:

Abe

Although obtaining an accurate representation of a stackup is
necessary when doing simulations I would not rely on the
extracted information to determine if a board passes SI.

I would use the ranges that were specified when the PCB
was designed to ensure that everything will work over all manufacturing
ranges (example dielectric of 4.1 to 4.7, trace width of
4.8 to 5.2 mils). The extracted information is only one of many
combinations permitted by the design.

Regards,

Patrick

>Dear Scholars:
>
> Probably most of you are well aware with how crucial stackup
>information is to a SI engineer. A comprehensive knowledge of design
>stackup can greatly contribute to the success and accuracy of a
>simulation task. Some fundamental questions regarding design stackup
>include:
>
> 1. The type, number and order of layers.
> 2. Do plane layers include any traces? do signal layers contain
>ground fills?
> 3. Are power planes split (i.e. multiple power such as +5.0 V and
>3.3 V) , or continuos (for instance single power +5.0 V) ?
> 4. Are ground or power planes meshed (hatched) or solid?
> 5. What are the values of substrate thickness and dielectric
>constant?
>
> It is of great importance for the SI engineer to have a detailed
>understanding of the stackup, so that he or she can input the simulator
>program with the most accurate data. Errors or inaccuracies in the
>stackup can result in a varying range of simulation problems which
>include:
>
> False impedance values
> Faulty waveforms and flight times
> Incompletely generated topology
> Halting of some simulation operations
>
> Stackup is usually provided to the SI staff by the circuit design
>engineer or the PCB designer. However, it is beneficial to know how to
>extract stackup information from various PCB databases. Allow me to
>elucidate this interesting concept with the aid of ALLEGRO and PADS
>databases, as well as QUAD's Intermediate Segment File (.isf).
>
> I. ALLEGRO DATABASES
>
> An ALLEGRO PCB database (i.e. a .brd file) can be viewed by an
>Allegro viewer program, freely available from the Cadence Web Site,
>which identifies and displays the stackup of the design. For example
>stackup of an eight layer board (consisting of four signal layers, three
>ground, and one power layer) using Allegro viewer, is identitfied as:
>
> TOP
> GND2
> INNER3
> VDD
> GND5
> INNER6
> GND7
> BOTTOM
>
> When extracting an Allegro database, I also examine the Layer.dat
>file ( an ASCII data file which results from the .brd file after
>execution of the Allegro EXTRACT utility batch program) for stackup
>details. For example, the following section of a Layer.dat file includes
>information regarding the thickness and dielectric constant of the Top
>layer, ground layer, an inner signal layer and substrate:
>
> S!1!TOP!POSTIVE!!YES!!595900mho/cm!COPPER!NO!3.98 w/cm-degC!1.2mil!
> S!2!!!NO!4.500000000000e+000!0 mho/cm!FR-4!!0.012 w/cm-degC! 8mil!
> S!3!GND2!NEGATIVE!EMBEDED_PLANE!YES!!595900 mho/cm!COPPER!YES!3.98
>w/cm-
> degC!1.2mil!
> S!4!!!!NO!4.500000000000e+000!0 mho/cm!FR-4!!0.012 w/cm-degC!8 mil!
> S!5!INNER3!POSITIVE!!YES!!595900 mho/cm!COPPER!NO!3.98 w/cm-degC!1.2
>mil!
>
> II. PADS DATABASES
>
> The PADS viewer program can be used to observe a PADS PCB database
>(.pcb) or ASCII file (.asc) and hence identify its stackup. Most
>PADS-power PCB databses that I have worked with have included up to 30
>layers consisting of several signal layers, several power and ground
>plane layers, primary and secondary solder paste, primary and secondary
>solder resist, primary and secondary assembly, annotation layer, etc.
>
> Frequently, it is the PADS .asc and not the PADS .pcb file which is
>inputted to the simulation program for extraction purposes. I usually
>review the PADS ASCII file for stackup content. An illustration is
>presented below:
>
> Layer5 = Ground
> 16837 7565 0.000 24 100 7
> Layer6 = Inner 2
> 16839 7432 0.000 24 100 7
> Layer 7 = + 5V, STB5V
> 16839 8732 0.000 24 100 7
>
> III.QUAD'S INTERMEDIATE SEGMENT FILE
>
> Information regarding the stackup of a design is also present in the
>Quad's Intermediate Segment File (.isf), as illustrated by the following
>example:
>
> N: 960DCLK2R
> S: 700700, 742500,695100,742500,0,6
> S:703700,743700,700700,742500,0,6
> S:69990,747900,703700,743700,11,6
> S:686500,745600,686500,759250,0,6
> S:686900,742500,686500,745600,0,6
> S:695100,742500,689600,742500,0,6
> V:703700,743700,3,111111111111
> P:TP459,1,1699900,747900,730,000000000001
> P:RP4,3,1,686500,759250,732,100000000000
> P:U11,14,1,695100,742500,690,110000000000
>
> Above describes a net (N: ), its associated segment (S: ), via (V: )
>and pads (P: ), as well as what layers they belong to, which also
>allows to examine connectivity.
>
> The main purpose of the Allegro layer.dat, PADS .asc and Quad .isf
>examples has been to illustrate that numerous files may contain
>important stackup details. In closing, stackup extraction involves
>obtaining information regarding design stackup from various files to
>check or to supplement the stackup diagrams often furnished by the
>design engineer or the PCB designer. The ultimate aim is to enables the
>SI engineer to input the simulator with the most accurate stackup,
>towards a smooth and reliable simulation.
>
> Like always, your comments are genuinely appreciated.
>
> Respectfully,
>
> Abe Riazi
> Anigma, Inc.
>
>
>
>
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>
>
**********************************************************************
Patrick Riffault
Cadence Design System (Canada)
613-726-2770
riffault@cadence.com
**********************************************************************

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