Re: [SI-LIST] : Anyone doing SI simulations for Pentium II boards?

D. C. Sessions (dc.sessions@vlsi.com)
Thu, 09 Sep 1999 07:26:53 -0700

Kim Helliwell wrote:
>
> I face the following puzzle in running a signal integrity
> simulation on Pentium II board. I'm using SpecctraQuest
> and Signoise, in case this matters.
>
> I have a Pentium II IBIS model (which I converted to Cadence's
> .dml format). This model appears to model all the parasitics
> of the Slot 1 board in a lumped manner; I presume that the
> model includes parasitics up to the edge fingers. (Does anyone
> know different?)
>
> I also have a model of a Slot 1 connector in SPICE format. Quite
> aside from issues of how this model is to be used (I'm trying to
> get the answer to that from the supplier) is the issue of how to
> include the Slot 1 connector parasitics in the simulation. At
> first, I thought I could use a design link and treat the connector
> as a cable connecting the main board and the Slot 1 module, but I
> think that requires that I have the "board layout" of the Pentium
> module. The next thought was to treat the connector as a package, but
> this doesn't work since the Pentium II module is already a package
> model. So I'm left with adding the connector parasitics in some
> fashion to the existing Pentium II model. I just want to check
> that this is in fact the correct approach, or else find out whether
> I'm giving up too soon on one of the first two approaches mentioned,
> or whether there's another approach I haven't considered.
>
> I'm sure I'm not the only one facing this, so how are others
> solving it?

If all you have is a lumped model of the Slot 1 module, the errors
introduced by your connector model are in the noise (as it were.)
Since the best you'll be able to get is crude approximations, you
might as well just add the lumped values for the connector to those
for the module and plan on doing the majority of your work in the lab.

-- 
D. C. Sessions
dc.sessions@vlsi.com

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