Re: [SI-LIST] : coming up with average power estimates for buffers

Adrian Shiner (adrian.shiner@virgin.net)
Tue, 03 Aug 1999 20:27:38 +0100

O'K for short time intervals and small systems. One of the problems with a large sytem consuming power on this scale is than it is dangerous to assume that you know the peak demand well from the study of relatively small samples.

I designed some air gapped, iron cored power frequency inductors using your principle many years ago, I have never seen similar in print. However, physical inductors corresponded to calculations well. One is still in use in my
arc welder.

Best wishes

Adrian

"S. Weir" wrote:

> Pat,
>
> If we deal in energy and time, then you can get an accurate answer for any
> circumstance: This is exactly the method which is required when designing
> systems such as switch-mode power supplies.
>
> Integrate V*I over time at each point of interest to obtain the energy
> drawn at said point, and perform the integration over your repeating
> interval. RMS is simply a way to obtain that value when the load is
> resistive, and only V or I is known. Since you now know the energy for
> some period of time at each point, you simply scale to seconds to obtain
> power, aka average. This works, because from a state-space averaging
> viewpoint, all the variations in voltage and current have been encapsulated
> in your integration interval. If you had a case where one pulse occurred
> every 100 cycles, then you would need to integrate 100 cycles. Since, your
> model is only a couple of cycles long at 50/50, that is all you need to
> integrate over.
>
> When evaluating heat loss in the ASIC's, remember to subtract out the power
> delivered to the loads. You will still need to account for the load power
> in your cabinet cooling budget.
>
> It sounds like your power cycle is very fast compared to any thermal time
> constants you are likely to have, and the duty cycle is high as well.
> Therefore, we can leave those effects to another time.
>
> I hope this helps.
>
> Regards,
>
> Steve.
>
> 2.
> At 10:32 AM 8/2/1999 -0700, you wrote:
> >RMS is the heating effect, so unless your thermal time constants can follow
> >the instantaneous values (doubtful), RMS should work.
> >
> >50 kW? Get rid of those vacuum tubes and use solid state! (couldn't resist)
> >
> >Larry Miller
> >
> >At 10:57 AM 8/2/99 -0500, you wrote:
> >>I'm working on a rather large system (over 50,000 Watts!), and we
> >>are trying to come up with some detailed power estimates for
> >>each component.
> >>
> >>The system is essentially comprised of LOTS(!) of identical
> >>parallel processing ASICs, each ASIC having roughly 600 I/O.
> >>The basic I/O is full-swing CMOS with a 2.5 VDD supply running
> >>at roughly 100 Mbps. A small change in one ASIC will have
> >>a three-orders of magnitude higher impact on the system, so we need
> >>to pay very close attention to details. The I/O have been
> >>designed and tweaked to account for impedance, edge rates,
> >>packaging effects, etc., so we have a high level of confidence
> >>they are going to work; at this point, we simply need to
> >>obtain a power estimate for them.
> >>
> >>In order to come up with good system-level power estimates (which
> >>will determine cooling requirements and power supply requirements),
> >>we need to have an accurate ASIC power estimate. We've got pretty
> >>good numbers for the core circuitry, but we're trying to develop
> >>an estimate for the custom I/O buffers.
> >>
> >>To get the power for one buffer, we simulate the buffer with
> >>a 1010101... pattern, toggling every possible bit period.
> >>The buffer is loaded with an average-length transmission
> >>line, and we use spice to plot the power vs time for at
> >>least two bit-transitions. Overall, we get a power
> >>vs time plot that is relatively flat except during the logic
> >>transitions (no surprise here), and the peaks vary in amplitude
> >>depending upon a rising or falling edge.
> >>
> >>In the past, we have used the "simple average" power, meaning
> >>taking the integral of the power over two bit periods (to ensure
> >>we've captured one falling and one rising edge)and dividing
> >>it by the time. We have used this figure as
> >>our average power for the worst-case-bit-pattern.
> >>
> >>However, a colleague recently suggested using the "RMS average"
> >>of the power, which is computed slightly differently. For our
> >>case, the RMS average resulted in a power estimate that was
> >>50% higher than the average value.
> >>
> >>>From my experience, taking the integral of the power curve will
> >>result in the effective energy consumed by the buffer, and dividing
> >>this by the time will provide the average power. However,
> >>RMS is used so frequently in power estimates, I could not provide
> >>a good answer why it shouldn't be used.
> >>
> >>Can anyone tell me how to best determine the average power
> >>for a buffer? Am I anywhere on the right track? Which is better,
> >>simple average or RMS average?
> >>
> >>One other point to note: as we increase the transmission line
> >>length, the RMS power goes up as well (as expected). However,
> >>this trend continues to a certain point, then the power actually
> >>reduces with increased line length. Can someone explain why
> >>the RMS power would be reduced with increased length? We're only
> >>seeing a small percentage change (~10-20%), but it's got
> >>me curious.
> >>
> >>
> >>Thanks,
> >>Pat Zabinski
> >>
> >>
> >>
> >>
> >>--
> >> Pat Zabinski ph: 507-284-5936
> >> Mayo Foundation fx: 507-284-9171
> >> 200 First Street SW zabinski.patrick@mayo.edu
> >> Rochester, MN 55905 www.mayo.edu/sppdg/sppdg_home_page.html
> >>
> >>
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