[SI-LIST] : Routing Criteria

Lum Wee Mei (lweemei@dso.org.sg)
Tue, 20 Jul 1999 11:41:18 +0800

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I have two questions which I hope you experts out there can enlighten
me.

Q1 : For years books have indicated that address and data bus must be
routed perpendicular to each other on different layers. However, with
board getting smaller and high component count, it will be a luxury to
do so, isn't it? As such, can I :

(a) Route address and data bus side by side on the same layer.
(b) If yes, how far apart must the address and data bus be separated.
(c) If no, can they be routed parallel to each other on adjacent layer.
(d) If no, can they be routed parallel to each other 2 layers away.
(e) How much clearance must be there for (b).
I would appreciate reasons or explanations be given for the answers to
the above questions.

Q2 : What is being practice is to route all clock signals with equal
length and no via (if possible) on a layer dedicated for them. This is
acheived by using those serpentine routing pattern. Can I :

(a) Start to introduce the serpentine routing pattern at the outputs.
(b) If yes, will there be any coupling between them.
(c) If no, how far apart must the next serpentine pattern be formed.
_ _ _
I I I I I I
I I I I I I
______ I I_I I_I I_____
_ _ _
I I I I I I
I I I I I I
______I I_I I_I I_____

Hope to hear from anyone of you and thanks in advance.
Regards.

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I have two questions which I hope you experts out there can enlighten me.

Q1 : For years books have indicated that address and data bus must be routed perpendicular to each other on different layers. However, with board getting smaller and high component count, it will be a luxury to do so, isn't it? As such, can I :

(a) Route address and data bus side by side on the same layer.
(b) If yes, how far apart must the address and data bus be separated.
(c) If no, can they be routed parallel to each other on adjacent layer.
(d) If no, can they be routed parallel to each other 2 layers away.
(e) How much clearance must be there for (b).
I would appreciate reasons or explanations be given for the answers to the above questions.

Q2 : What is being practice is to route all clock signals with equal length and no via (if possible) on a layer dedicated for them. This is acheived by using those serpentine routing pattern. Can I :

(a) Start to introduce the serpentine routing pattern at the outputs.
(b) If yes, will there be any coupling between them.
(c) If no, how far apart must the next serpentine pattern be formed.
           _    _   _
           I I  I  I  I I
           I I  I  I  I I
______ I I_I  I_I I_____
           _    _    _
          I  I  I  I  I  I
          I  I  I  I  I  I
______I  I_I  I_I  I_____

Hope to hear from anyone of you and thanks in advance.
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